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Fedora ARM Secondary Architecture/SheevaPlug

160 bytes added, 16:11, 16 April 2010
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# == '''SheevaPlug Specifications''' ==
# '''Sheeva CPU Core'''
# 1.2 GHz operationL1 Cache: 16K Instruction + 16K DataL2 Cache: 256KB
Memory# L1 Cache: 16K Instruction + 16K Data
DDR2 400MHz, 16-bit bus512MB DDR2# L2 Cache: 1Gb x8, 4 devicesPower efficient Samsung devicesNAND FLASH Controller, 8-bit bus512MB NAND FLASH: 4Gb x8, direct boot128-bit eFuse Memory256KB
Power # '''Memory'''
Power input: 100# DDR2 400MHz, 16-240VAC/50-60Hz 19WDC Consumption: 5V/3.0AHigh efficiency POL DC-DC convertersDevelopment Interfacebit bus
System Development BoardJTAG and Console Interface via USBSDIO expansionJTAG OpenOCD support via USBHigh speed I/O & Peripherals# 512MB DDR2: 1Gb x8, 4 devices
# Power efficient Samsung devices # NAND FLASH Controller, 8-bit bus # 512MB NAND FLASH: 4Gb x8, direct boot # 128-bit eFuse Memory   # '''Power # ''' #* Power input: 100-240VAC/50-60Hz 19W# DC Consumption: 5V/3.0A#* High efficiency POL DC-DC converters  # <div>'''Development Interface # '''</div> #* System Development Board#* JTAG and Console Interface via USB#* SDIO expansion#* JTAG OpenOCD support via USB # <div>'''High speed I/O & Peripherals '''</div> #* GE, USB 2.0 Host#* RTC w/ Battery # <font color="#000000">'''UL/CE/FCC certified'''</font>

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