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→False Sharing
Now that we understand the basics of a cache, how does this relate to the concept of false sharing? [[File:CPUCacheline.png|thumb|400px|Cache line sharing.]]
False sharing occurs when multiple processors modify data that resides on the same cache line. When this data is written back to memory, the shared cache lines are marked as invalid or dirty. Processors must fetch an updated copy introducing from memory resulting in significant delays due to memory access speeds. As you increase the number of processorsIf false sharing is not minimized, this issue quickly spirals out of control as there is an when increasing chance the cache line is invalidnumber of processors.
The key thing to note is that you do not need to modify the same piece of data. If the modified data happens to belong to the same cache line, the cache will be invalidated, forcing a memory update to maintain cache coherency.
