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Created page with "Category:Fall 2019 SPO600 This is the schedule and main index page for the SPO600 ''Software Portability and Optimization'' course for Winter 2020. <!-- {{Admon/import..."
[[Category:Fall 2019 SPO600]]
This is the schedule and main index page for the [[SPO600]] ''Software Portability and Optimization'' course for Winter 2020.
<!-- {{Admon/important|It's Alive!|This [[SPO600]] weekly schedule will be updated as the course proceeds - dates and content are subject to change. The cells in the summary table will be linked to relevant resources and labs as the course progresses.}} -->
{{Admon/important|Content being Updated|This page is in the process of being updated from a previous semester's content. It is not yet updated for the current semester. Do not rely on the accuracy of this information until this warning is removed.}}
<!-- {{Admon/obsolete|[[Current SPO600 Weekly Schedule]]}} -->
== Schedule Summary Table ==
This is a summary/index table. Please follow the links in each cell for additional detail which will be added below as the course proceeds -- especially for the ''Deliverables'' column.
{|cellspacing="0" width="100%" cellpadding="5" border="1" style="background: #e0e0ff"
|-
!Week!!Week of...!!width="28%"|Class I<br/>Tuesday 1:30-3:15<br />Room B1024!!width="28%"|Class II<br/>Friday 11:40-1:25<br />Room K1263!!width="28%"|Deliverables<br/>(Summary - click for details)
|-
|1||Jan 06||[[#Week 1 - Class I|Introduction to the Course / Introduction to the Problem / How is code accepted into an open source project? (Homework: Lab 1)]]||[[#Week 1 - Class II|Computer architecture basics / Binary Representation of Data / Introduction to Assembly Language]]||[[#Week 1 Deliverables|Set up for the course]]
|-
|2||Jan 13||[[#Week 2 - Class I|6502 Assembly Basics Lab (Lab 2)]]||[[#Week 2 - Class II|Assembly language conventions and Examples / Project Selection]]||[[#Week 2 Deliverables|Lab 1 and 2]]
|-
|3||Jan 20||[[#Week 3 - Class I|6502 Strings and Memory Lab (Lab 3)]]||[[#Week 3 - Class II|Computer math / Building Code]]||[[#Week 3 Deliverables|Lab 3, Selected Project]]
|-
|4||Jan 27||[[#Week 4 - Class I|6502 Math Lab (Lab 4)]]||[[#Week 4 - Class II|System routines / Sysadmin for Devs]]||[[#Week 4 Deliverables|Lab 4, Project Build]]
|-
|5||Feb 03||[[#Week 5 - Class I|6502 Application Lab (Lab 5)]]||[[#Week 5 - Class II|Introduction to x86_64 and AArch64 architectures]]||[[#Week 5 Deliverables|Lab 5]]
|-
|6||Feb 10||[[#Week 6 - Class I|64-bit Assembly Language Lab (Lab 6)]]||[[#Week 6 - Class II|Profiling]]||[[#Week 6 Deliverables|Lab 6]]
|-
|7||Feb 17||[[#Week 7 - Class I|Profiling Lab (Lab 7)]]||[[#Week 7 - Class II|Project Stage 1]]||[[#Week 7 Deliverables|Lab 7, Project Profiling]]
|-
|Reading||Feb 24||style="background: #f0f0ff" colspan="5" align="center"|Reading Week
|-
|8||Mar 02||[[#Week 8 - Class I|Algorithm Selection Lab (Lab 8)]]||[[#Week 8 - Class II|SIMD and Vectorization]]||[[#Week 8 Deliverables|Project Stage 1 due]]
|-
|9||Mar 09||[[#Week 9 - Class I|SIMD Lab (Lab 9)]]||[[#Week 9 - Class II|Identifying Optimization Opportunities]]||[[#Week 9 Deliverables|Lab 9]]
|-
|10||Mar 16||[[#Week 10 - Class I|Atomics]]||[[#Week 10 - Class II|Project Discussion]]||[[#Week 10 Deliverables|Project Work]]
|-
|11||Mar 23||[[#Week 11 - Class I|Project Hacking]]||[[#Week 11 - Class II|Memory Ordering, Synchronization, and Barriers]]||[[#Week 11 Deliverables|Project Stage 2 due]]
|-
|12||Mar 30||[[#Week 12 - Class I|ifunc]]||[[#Week 12 - Class II|Emerging directions in system architecture]]||[[#Week 12 Deliverables|Project Work]]
|-
|13||Apr 06||[[#Week 13 - Class I|Demos]]||[[#Week 13 - Class II|Course wrap-up discussion]]||[[#Week 13 Deliverables|Project Stage 3 due]]
|-
|}
== Week 1 ==
=== Week 1 - Class I ===
==== Introduction to the Problems ====
===== Porting and Portability =====
* Most software is written in a '''high-level language''' which can be compiled into [[Machine Language|machine code]] for a specific computer architecture. In many cases, this code can be compiled for multiple architectures. However, there is a lot of existing code that contains some architecture-specific code fragments written in architecture-specific high-level code or in [[Assembly Language]].
* Reasons that code is architecture-specific:
** System assumptions that don't hold true on other platforms
*** Variable or [[Word|word]] size
*** [[Endian|Endianness]]
** Code that takes advantage of platform-specific features
* Reasons for writing code in Assembly Langauge include:
** Performance
** [[Atomic Operation|Atomic Operations]]
** Direct access to hardware features, e.g., CPUID registers
* Most of the historical reasons for including assembler are no longer valid. Modern compilers can out-perform most hand-optimized assembly code, atomic operations can be handled by libraries or [[Compiler Intrinsics|compiler intrinsics]], and most hardware access should be performed through the operating system or appropriate libraries.
* A new architecture has appeared: AArch64, which is part of [http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php ARMv8]. This is the first new [[Computer Architecture|computer architecture]] to appear in several years (at least, the first mainstream computer architecture).
* At this point, most key open source software (the software typically present in a Linux distribution such as Ubuntu or Fedora, for example) now runs on AArch64. However, it may not run as well as on older architectures (such as x86_64).
===== Benchmarking and Profiling =====
Benchmarking involves testing software performance under controlled conditions so that the performance can be compared to other software, the same software operating on other types of computers, or so that the impact of a change to the software can be gauged.
Profiling is the process of analyzing software performance on finer scale, determining resource usage per program part (typically per function/method). This can identify software bottlenecks and potential targets for optimization.
===== Optimization =====
Optimization is the process of evaluating different ways that software can be written or built and selecting the option that has the best performance tradeoffs.
Optimization may involve substituting software algorithms, altering the sequence of operations, using architecture-specific code, or altering the build process. It is important to ensure that the optimized software produces correct results and does not cause an unacceptable performance regression for other use-cases, system configurations, operating systems, or architectures.
The definition of "performance" varies according to the target system and the operating goals. For example, in some contexts, low memory or storage usage is important; in other cases, fast operation; and in other cases, low CPU utilization or long battery life may be the most important factor. It is often possible to trade off performance in one area for another; using a lookup table, for example, can reduce CPU utilization and improve battery life in some algorithms, in return for increased memory consumption.
Most advanced compilers perform some level of optimization, and the options selected for compilation can have a significant effect on the trade-offs made by the compiler, affecting memory usage, execution speed, executable size, power consumption, and debuggability.
===== Build Process =====
Building software is a complex task that many developers gloss over. The simple act of compiling a program invokes a process with five or more stages, including pre-proccessing, compiling, optimizing, assembling, and linking. However, a complex software system will have hundreds or even thousands of source files, as well as dozens or hundreds of build configuration options, auto configuration scripts (cmake, autotools), build scripts (such as Makefiles) to coordinate the process, test suites, and more.
The build process varies significantly between software packages. Most software distribution projects (including Linux distributions such as Ubuntu and Fedora) use a packaging system that further wraps the build process in a standardized script format, so that different software packages can be built using a consistent process.
In order to get consistent and comparable benchmark results, you need to ensure that the software is being built in a consistent way. Altering the build process is one way of optimizing software.
Note that the build time for a complex package can range up to hours or even days!
==== General Course Information ====
* Course resources are linked from the CDOT wiki, starting at https://wiki.cdot.senecacollege.ca/wiki/SPO600 (Quick find: This page will usually be Google's top result for a search on "SPO600").
* Coursework is submitted by blogging.
* Quizzes will be short (1 page) and will be held without announcement at any time, generally at the start of class. There is no opportunity to re-take a missed quiz, but your lowest three quiz scores will not be counted, so do not worry if you miss one or two.
** Students with test accommodations: an alternate monthly quiz is available in the Test Centre. See the professor for details.
* Course marks (see Weekly Schedule for dates):
** 60% - Project Deliverables
** 20% - Communication (Blog and Wiki writing)
** 20% - Labs and Quizzes (10% labs - completed/not completed; 10% for quizzes - lowest 3 scores not counted)
* Classes will be held in an [[Active Learning Classroom]] -- you are encouraged to bring your own laptop to class. If you do not have a laptop, consider signing one out of the Learning Commons for class, or using a smartphone with an HDMI adapter.
* For more course information, refer to the SPO600 Weekly Schedule (this page), the [http://www.senecacollege.ca/ssos/findWithoutSemester/spo600/sict Course Outline], and [[SPO600 Course Policies]].
==== Course and Setup: Accounts, agreements, servers, and more ====
* [[SPO600 Communication Tools]]
* [[Fall 2019 SPO600 Participants]] page
* [[SPO600_Servers#Preparatory_Steps|Key generation]] for [[SSH]] to the [[SPO600 Servers]].
==== How open source communities work ====
* Do the [[SPO600 Code Review Lab|Code Review Lab (Lab 1)]] as homework.
=== Week 1 - Class II ===
* Compiler Operation
** Stages of Compilation
**# Preprocessing
**# Compiling
**# Assembling
**# Linking
* Analyzing compiler output
** Disassembly
* [[SPO600 Compiled C Lab|Compiled C Lab]] (Lab 2)
=== Week 1 Deliverables ===
# Course setup:
## Set up your [[SPO600 Communication Tools]] - in particular, set up a blog and add it to [http://zenit.senecac.on.ca/~chris.tyler/planet/ Planet CDOT] (via the [[Planet CDOT Feed List]]).
## Add yourself to the [[Current SPO600 Participants]] page (leave the projects columns blank).
## Generate a [[SPO600_Servers#Preparatory_Steps|pair of keys]] for [[SSH]] and email the public key to your professor, so that he can set up your access to the [[SPO600 Servers|class servers]].
## Optional (strongly recommended): [[SPO600 Host Setup|Set up a personal Linux system]].
## Optional: Purchase an AArch64 development board (such as a [http://96boards.org 96Boards] HiKey or Raspberry Pi 3 or 4. (If you use a Pi, install a 64-bit Linux operating system on it, not a 32-bit version).
# Complete [[SPO600 Code Review Lab|Lab 1]] and write it up on your blog.
== Week 2 ==
=== Week 2 - Class I ===
* [[Make and Makefiles]]
* [[Assembly Language]]
* [[SPO600 Assembler Lab|Assembler Lab]] (Lab 3)
=== Week 2 - Class II ===
* [[SPO600 Assembler Lab|Assembler Lab]] (Lab 3)
=== Week 2 Deliverables ===
* Blog your results and conclusion to [[SPO600 Code Review Lab|Code Review Lab (Lab 1)]] and [[SPO600 Compiled C Lab|Compiled C Lab (Lab 2)]]
* Blog about your initial work on [[SPO600 Assembler Lab|Lab 3]].
* Set up your account on the [[SPO600_Communication_Tools#Slack|Seneca Open Source Slack Workspace]].
== Week 3 ==
=== Week 3 - Class I ===
* ''Sysadmin for Devs''
** In-class discussion of tips and tricks for efficient work on a Linux server
=== Week 3 - Class II ===
* Finish [[SPO600 Assembler Lab|Lab 3]]
=== Week 3 - Deliverables ===
* Finish and blog your detailed results for the [[SPO600 Assembler Lab|Assembler Lab]] (Lab 3)
== Week 4 ==
=== Week 4 - Class I ===
* Binary Representation of Data
** Integers
*** Integers are the basic building block of binary numbers.
*** In an unsigned integer, the bits are numbered from right to left starting at 0, and the value of each bit is <code>2<sup>bit</sup></code>. The value represented is the sum of each bit multiplied by its corresponding bit value. The range of an unsigned integer is <code>0:2<sup>bits</sup>-1</code> where bits is the number of bits in the unsigned integer.
*** Signed integers are generally stored in twos-complement format, where the highest bit is used as a sign bit. If that bit is set, the value represented is <code>-(!value)-1</code> where ! is the NOT operation (each bit gets flipped from 0→1 and 1→2)
** Fixed-point
*** A fixed-point value is encoded the same as an integer, except that some of the bits are fractional -- they're considered to be to the right of the "binary point" (binary version of "decimal point" - or more generically, the ''radix point''). For example, binary 000001.00 is decimal 1.0, and 000001.11 is decimal 1.75.
*** An alternative to fixed-point values is integer values in a smaller unit of measurement. For example, some accounting software may use integer values representing cents. For input and display purposes, dollar and cent values are converted to/from cent values.
** Floating-point
*** Floating point numbers have three parts: a ''sign bit'' (0 for positive, 1 for negative), a ''mantissa'' or ''significand'', and an ''exponent''. The value is interpreted as <code>''sign'' mantissa * 2<sup>exponent</sup></code>.
** Sound
** Graphics
** Compression techniques
*** Huffman encoding / Adaptive arithmetic encoding
*** Repeated sequence encoding (1D, 2D, 3D)
*** Decomposition
*** Pallettization
*** Psychoacoustic and psychovisual compression
* Problem: Scaling Sound
** Naive approach
** Lookup table
** Fixed-point multiply and shift
=== Week 4 - Class II ===
* [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab]] (Lab 4)
=== Week 4 Deliverables ===
* Blog your results to [[SPO600 Algorithm Selection Lab|Lab 4]]
== Week 5 ==
=== Week 5 - Class I ===
* SIMD
** SIMD is an acronym for "Single Instruction, Multiple Data", and refers to a class of instructions which perform the same operation on several separate pieces of data in parallel. SIMD instructions also include related instructions to set up data for SIMD processing, and to summarize results.
** SIMD is based on very wide registers (128 bits to 2048 bits on implementations current as of 2019), and these wide registers can be treated as multiple "lanes" of similar data. These SIMD registers, also called vector registers, can therefore be thought of as small arrays of values.
** A 128-bit SIMD register can be used as:
*** two 64-bit lanes
*** four 32-bit lanes
*** eight 16-bit lanes
*** sixteen 8-bit lanes
** Each architecture has a different notation for SIMD registers. In AArch64 (which will be our focus):
*** Vector usage uses the notation v''n''.''s'' where ''n'' is the register number and ''s'' is the shape of the lanes, expressed as the number of lanes and a letter indicating the width of the lanes: q for quad-word (128 bits), d for double-word (64 bits), s for single-word (32 bits), h for half-word (16 bits), and b for byte (8 bits). Therefore, <code>v0.16b</code> is vector register 0 used as 16 lanes of 8 bits (1 byte) each, while <code>v8.4s</code> is vector register 8 used as 4 lanes of 32 bits each. Most instructions permit either 64 or 128 bits of the register to be used.
*** Scalar usage uses the lane width letter followed by the vector register number. Therefore, <code>q3</code> refers to vector register 3 used as a single 128-bit value, and <code>s3</code> refers to the same register used as a single 32-bit register. Note that these are the same register referred to as v3 for vector usage. When using less than 128 bits, the remaining bits are either zero-filled (unsigned usage) or sign-extended (signed usage: the upper bits are filled with the sign bit, i.e., the same value as the high bit of the active part of the register).
** Most SIMD operations work on corresponding lanes of the operand registers. For example, the AArch64 instruction <code>add v0.8h, v1.8h, v2.8h</code> will take the value in the first lane of register 1, add the value in the first lane of register 2, and place the result in the first lane of register 0. At the same time, the other lanes are processed in the same way, resulting in 8 simultaneous addition operations being performed.
** A small number of SIMD operations work across lanes, e.g., to find the lowest or highest value in all of the lanes, to add the lanes together, or to duplicate a single value into all of the lanes of a register. These are usually used to set up or summarize the results of SIMD operations -- for example, a value of 0 might be duplicated into all of the lanes of a result register, then a loop applied to sum array data into the results register, and then a lane-summing operation performed to merge the results from all of the lanes.
* SIMD capabilities can be used in a program in one of three different ways:
*# The compiler's ''auto-vectorizer'' can be used to identify sections of code to which SIMD is applicable, and SIMD code will automatically be generated.
*#* This works for the basic SIMD operations, but may not be applicable to advanced SIMD instructions, which don't clearly map to C statements.
*#* The compiler will be very cautious about vectorizing code. See the Resources section below for insight into these challenges.
*#** In order to vectorize a loop, among other things, the number of loop iterations needs to be known before the loop starts, memory layout must meet SIMD alignment requirements, loops must not overlap in a way that is affected by vectorization.
*#** The compiler will also calculate a cost for the vectorization: in the case of a small loop, the extra setup before the loop and processing after the loop may negate the benefits of vectorization.
*#* Vectorization in applied by default only at the -O3 level in most compilers. In GCC:
*#** The main individual feature flag to turn on vectorization is <code>-ftree-vectorize</code> (enabled by default at -O3, disabled at other levels).
*#** You can see all of the vectorization decisions using <code>-fopt-info-vec-all</code> or you can see just the missed vectorizations using <code>-fopt-info-vec-missed</code> (which is usually what you want to focus on, because it show only the loops where vectorization was ''not'' enabled, and the reason that it was not). This approach is generally very portable.
*# We can explicitly include SIMD instructions in a C program by using [[Inline Assembly Language|Inline Assembler]]. This is obviously architecture-specific, so it is important to use C preprocessor directives to include/exclude this code depending on the platform for which it is compiled, and to use a generic C implementation on any platform for which you are not providing an inline assembler version.
*# ''C Intrinsics'' are function-like extensions to the C language. Although they look like functions, they are compiled inline, and they are used to provide access to features which are not provided by the C language itself. There is a group of intrinsics which provide access to SIMD instructions. However, the benefit of using these over inline assembler is debatable. SIMD intrinsics are not portable, and should be included with C preprocessor directives like inline assembler.
=== Week 5 - Class II ===
* [[SPO600 SIMD Lab]] (Lab 5)
=== Week 5 Resources ===
==== Auto-vectorization ====
* [https://gcc.gnu.org/projects/tree-ssa/vectorization.html Auto-Vectorization in GCC] - Main project page for the GCC auto-vectorizer.
* [http://locklessinc.com/articles/vectorize/ Auto-vectorization with gcc 4.7] - An excellent discussion of the capabilities and limitations of the GCC auto-vectorizer, intrinsics for providing hints to GCC, and other code pattern changes that can improve results. Note that there has been some improvement in the auto-vectorizer since this article was written. '''This article is strongly recommended.'''
* [https://software.intel.com/sites/default/files/8c/a9/CompilerAutovectorizationGuide.pdf Intel (Auto)Vectorization Tutorial] - this deals with the Intel compiler (ICC) but the general technical discussion is valid for other compilers such as gcc and llvm
==== Inline Assembly Language ====
* [[Inline Assembly Language]]
* [http://developer.arm.com ARM Developer Information Centre]
** [https://developer.arm.com/products/architecture/a-profile/docs/den0024/a ARM Cortex-A Series Programmer’s Guide for ARMv8-A]
* The ''short'' guide to the ARMv8 instruction set: [https://www.element14.com/community/servlet/JiveServlet/previewBody/41836-102-1-229511/ARM.Reference_Manual.pdf ARMv8 Instruction Set Overview] ("ARM ISA Overview")
* The ''long'' guide to the ARMv8 instruction set: [https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile] ("ARM ARM")
==== C Intrinsics - AArch64 SIMD ====
* [https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics ARM NEON Intrinsics Reference]
* [https://gcc.gnu.org/onlinedocs/gcc/ARM-C-Language-Extensions-_0028ACLE_0029.html GCC ARM C Language Extensions]
=== Week 5 Deliverables ===
* Blog about the SIMD Lab
== Week 6 ==
=== Week 6 - Class I ===
* [[Compiler Optimizations]]
* Advanced Compiler Optimizations
** [[Profile Guided Optimization]]
** [[Link Time Optimization]]
* [[Profiling]]
=== Week 6 - Class II ===
* Continue work on the [[SPO600 SIMD Lab|SIMD Lab]] (Lab 5)
=== Week 6 Deliverables ===
* Blog about your results to Lab 5
== Week 7 ==
=== Week 7 - Class I ===
Building software...
* Configuration Systems
** make-based systems
*** [https://www.gnu.org/software/automake/manual/html_node/index.html The GNU Build System: autotools, autoconf, automake]
**** GNU autotools makes extensive use of the ''configuration name'' ("triplet") -- ''cpu-manufacturer-operatingSystem'' or ''cpu-manufacturer-kernel-operatingSystem'' (e.g.,
**** config.guess and config.sub
*** CMake
*** qmake
*** Meson
*** iMake and Others
** Non-make-based systems
*** Apache Ant
*** Apache Maven
*** Qt Build System
* Building in the Source Tree vs. Building in a Parallel Tree
** Pros and Cons
** [https://www.gnu.org/software/automake/manual/html_node/VPATH-Builds.html#VPATH-Builds GNU automake ''vpath'' builds]
* Installing and Testing in non-system directories
** Configuring installation to a non-standard directory
*** Running <code>configure</code> with <code>--prefix</code>
*** Running <code>make install</code> as a non-root user
*** DESTDIR variable for <code>make install</code>
** Runtime environment variables:
*** PATH
*** LD_LIBRARY_PATH and LD_PRELOAD (see the [http://man7.org/linux/man-pages/man8/ld.so.8.html ld.so manpage])
** Security when running software
*** Device access
**** Opening a TCP/IP or UDP/IP port below 1024
**** Accessing a <code>/dev</code> device entry
***** Root permission
***** Group permission
*** SELinux Type Enforcement
**** Enforcement mode
***** View enforcement mode: <code>getenforce</code>
***** Set enforcement mode: <code>setenforce</code>
**** Changing policy
***** [https://fedoraproject.org/wiki/SELinux/audit2why audit2why]
***** [https://fedoraproject.org/wiki/SELinux/audit2why audit2allow]
* Build Dependencies
* Packaging
* General information about the SPO600 projects
** Goal
** Stages
** Approaching the Project
=== Week 7 - Class II ===
* [[Fall 2019 SPO600 Project|Project Selection]]
=== Week 7 Deliverables ===
* Catch up on any incomplete labs (and blog about them)
* Blog about your project selection progress
== Week 8 ==
=== Week 8 - Class I ===
==== Overview/Review of Processor Operation ====
* Fetch-decode-dispatch-execute cycle
* Pipelining
* Branch Prediction
* In-order vs. Out-of-order execution
** Micro-ops
==== Memory Basics ====
* Organization of Memory
** Process organization
*** Text, data
*** Stack
*** Heap
** System organization
*** Kernel memory in process maps
*** Use of unallocated memory for buffers and cache
* Memory Speeds
* Cache
** Cache lookup
** Cache synchronization and invalidation
** Cache line size
* Prefetch
** Prefetch hinting
==== Memory Architecture ====
* Virtual Memory and Memory Management Units (MMUs)
** General principles of Virtual Memory and operation of MMUs
** Memory protection
*** Unmapped Regions
*** Write Protection
*** Execute Protection
*** Privilege Levels
** Swapping
** Text sharing
** Demand Loading
** Data sharing
*** Shared memory for Inter-Process Communication
*** Copy-on-Write (CoW)
** Memory mapped files
==== Memory Statistics ====
* Resident Set Size (RSS) and Virtual Set Size (VSS)
* Total memory consumption per process
* Total system memory consumption
==== Software Impact ====
* Alignment checks
* Page boundary crossing
=== Week 8 - Class II ===
* Project Discussion
=== Week 8 Deliverables ===
* Blog about your project work
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== Week 2 ==
=== Week 2 - Class I ===
* Sysadmin for Developers
* Building Code
** [[Make and Makefiles]]
** [[SPO600 Code Building Lab|Code Building Lab]] (Lab 2)
=== Week 2 - Class II ===
* Compiler Operation
** Stages of Compilation
**# Preprocessing
**# Compiling
**# Assembling
**# Linking
* Analyzing compiler output
** Disassembly
* [[SPO600 Compiled C Lab|Compiled C Lab]] (Lab 3)
=== Week 2 Deliverables ===
* Blog your conclusion to the [[SPO600 Code Review Lab|Code Review Lab (Lab 1)]]
* Blog the results and conclusion from the [[SPO600 Code Building Lab|Compiled C Lab (Lab 2)]]
* Blog the results and conclusion from the [[SPO600 Compiled C Lab|Compiled C Lab (Lab 3)]]
== Week 3 ==
=== Week 3 - Class I ===
* [[Make and Makefiles]]
* [[Assembly Language]]
* [[SPO600 Assembler Lab|Assembler Lab]] (Lab 4)
=== Week 3 - Class II ===
* [[SPO600 Assembler Lab|Assembler Lab]] (Lab 4) Continued...
=== Week 3 Deliverables ===
* Blog about [[SPO600 Assembler Lab|Lab 4]].
== Week 4 ==
=== Week 4 - Class I ===
* [[SPO600 Assembler Lab|Assembler Lab]] (Lab 4) Wrap-up...
* Binary Representation of Data
** Integers
** Fixed-point
** Floating-point
** Sound
** Graphics
** Compression techniques
*** Huffman encoding / Adaptive arithmetic encoding
*** Repeated sequence encoding (1D, 2D, 3D)
*** Decomposition
*** Pallettization
*** Psychoacoustic and psychovisual compression
=== Week 4 - Class II ===
* [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab]] (Lab 5)
=== Week 4 Deliverables ===
* Blog your results to [[SPO600 Assembler Lab|Lab 4]]
== Week 5 ==
=== Week 5 - Class I ===
'''Note:''' Your prof is away!
* Investigate various tools available for [[Profiling]]
** Ensure that you know how to use <code>gprof</code>
** Ensure that you know how to use at least one other Linux profiling tool
** Blog about it, including the example of profiling the sound scaling programs from [[SPO600 Algorithm Selection Lab|Lab 5]]
=== Week 5 - Class II ===
* SIMD and Auto-vectorization
* [[Inline Assembly Language|Inline Assembler]]
* C Intrinsics
* [[SPO600 Vectorization Lab|Vectorization Lab]] (Optional lab - recommended)
=== Week 5 Deliverables ===
* Blog your Profiling investigation results
* Optional: Blog about the Vectorization Lab if you performed it
== Week 6 ==
=== Week 6 - Class I ===
* Thanksgiving -- enjoy time with your friends and family!
** No class
=== Week 6 - Class II ===
* '''Note: Your prof is away'''
** Room is available to collaborate if desired -- AV unlock code is 2598
* Perform the [[SPO600 Inline Assembler Lab|Inline Assembler Lab]] (Lab 6)
=== Week 6 Deliverables ===
* Blog your results to the [[SPO600 Inline Assembler Lab|Inline Assembler Lab]] (Lab 6)
== Week 7 ==
=== Week 7 - Class I ===
* Discussion
=== Week 7 - Class II ===
* Discussion
=== Week 7 Deliverables ===
* Wrap up any labs not yet completed.
== Week 8 ==
=== Week 8 - Class I ===
* [[Fall 2018 SPO600 Project]]
=== Week 8 - Class II ===
* Project Discussion
=== Week 8 Deliverables ===
* Blog about your project.
== Week 2 ==
=== Week 2 - Class I ===
* Binary Representation of Data
** Numbers
*** Integers
*** Fixed-point numbers
*** Floating-point numbers
** Characters
*** ASCII
*** ISO8859-1
*** Unicode
**** Encoding schemes
*** EBCDIC
** Images
** Sound
* [[Computer Architecture]] overview (see also the [[:Category:Computer Architecture|Computer Architecture Category]])
* A first look at the x86_64 and AArch64 Architectures and ISA
** Register file comparison
** Instruction encoding
** ELF
** Procedure calling conventions
==== Reference ====
* [[Computer Architecture]] and [[:Category:Computer Architecture|Computer Architecture Category]]
* [[Aarch64 Register and Instruction Quick Start]]
* [[x86_64 Register and Instruction Quick Start]]
=== Week 2 - Class II ===
* Compiler Operation
** Stages of Compilation
**# Preprocessing
**# Compiling
**# Assembling
**# Linking
* Analyzing compiler output
** Disassembly
* [[SPO600 Compiled C Lab|Compiled C Lab (Lab 2)]]
=== Week 2 Deliverables ===
* Blog your conclusion to the [[SPO600 Code Review Lab|Code Review Lab (Lab 1)]]
* Blog the results and conclusion from the [[SPO600 Compiled C Lab|Compiled C Lab (Lab 2)]]
== Week 3 ==
=== Week 3 - Class I ===
* [[Assembler Basics]]
* [[Syscalls]]
* [[SPO600 Assembler Lab|Assembler Lab (Lab 3)]].
=== Week 3 - Class II ===
* <strike>Complete Lab 3</strike> <span style="color: #ff0000">Class cancelled</span>
=== Week 3 Deliverables ===
* Blog your initial experience on the [[SPO600 Assembler Lab|Assembler Lab (Lab 3)]].
== Week 4 ==
=== Week 4 - Class I ===
* Continue work in class on the [[SPO600 Assembler Lab|Assembler Lab (Lab 3)]].
=== Week 4 - Class II ===
* Continue work in class on the [[SPO600 Assembler Lab|Assembler Lab (Lab 3)]].
=== Week 4 Deliverables ===
* Blog your [[Lab 3]] results.
== Week 5 ==
=== Week 5 - Class I ===
* [[Compiler Optimizations]]
=== Week 5 - Class II ===
* Advanced Compiler Optimizations
** [[Profile Guided Optimization]]
** [[Link Time Optimization]]
* Introduction to Vector Processing/SIMD
** [[SPO600 Vectorization Lab|Vectorization Lab]] (Lab 4) as homework
* [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab]] (Lab 5) in work groups
=== Week 5 Deliverables ===
* Blog your results for [[SPO600 Vectorization Lab|Lab 4]] and [[SPO600 Algorithm Selection Lab|Lab 5]] -- be sure to include links to your code, detailed results, and your reflection on the lab.
== Week 6 ==
=== Week 6 - Class I ===
* [[Inline Assembly Language]] -- often used for:
*# Implementing a memory barrier
*# Performing an [[Atomic Operation]]
*#* '''Atomics''' are operations which must be completed in a single step (or appear to be completed in a single step) without potential interruption.
*#* Wikipedia has a good basic overview of the need for atomicity in the article on [http://en.wikipedia.org/wiki/Linearizability Linearizability]
*# Gaining performance (by accessing processor features not exposed by the high-level language being used (C, C++, ...))
* [[SPO600 Inline Assembler Lab|Inline Assembler Lab]] (Lab 6)
=== Week 6 - Class II ===
* [[Addressing Mode|Processor Addressing Modes]]
* Navigating CPU technical documentation
* A (very) quick intro to GDB
* [[Winter 2018 SPO600 Project|Project]]: Selecting, Building, Benchmarking, and Profiling
=== Week 6 Deliverables ===
* Blog your Lab 5 and 6 results.
* Start blogging about your project.
* '''Reminder:''' Blogs will be marked as they stand at 11:59 on March 4, the Sunday at the end of Reading Week.
== Week 7 ==
=== Week 7 - Class I ===
* Project Discussion
=== Week 7 - Class II ===
* [[Profiling]]
=== Week 7 Deliverables ===
* Complete your [[Winter_2018_SPO600_Project#Stage_1|Stage I]] project posts on your blog.
== Week 8 ==
=== Week 8 - Class I ===
* Sysadmin for Developers
* Project Discussion
=== Week 8 - Class II ===
==== Overview/Review of Processor Operation ====
* Fetch-decode-dispatch-execute cycle
* Pipelining
* Branch Prediction
* In-order vs. Out-of-order execution
** Micro-ops
==== Memory Basics ====
* Organization of Memory
** Process organization
*** Text, data
*** Stack
*** Heap
** System organization
* Memory Speeds
* Cache
** Cache lookup
** Cache synchronization and invalidation
** Cache line size
* Prefetch
** Prefetch hinting
==== Memory Architecture ====
* Virtual Memory and Memory Management Units (MMUs)
** General principles of Virtual Memory and operation of MMUs
** Memory protection
*** Unmapped Regions
*** Write Protection
*** Execute Protection
*** Privilege Levels
** Swapping
** Text sharing
** Demand Loading
** Data sharing
*** Shared memory for Inter-Process Communication
*** Copy-on-Write (CoW)
** Memory mapped files
=== Software Impact ===
* Alignment checks
* Page boundary crossing
=== Week 8 Delivarables ===
* Blog about your project
== Week 9 ==
=== Week 9 - Class I ===
==== Atomics ====
* '''Atomics''' are operations which must be completed in a single step (or appear to be completed in a single step) without potential interruption.
** Wikipedia has a good basic overview of the need for atomicity in the article on [http://en.wikipedia.org/wiki/Linearizability Linerarizability]
** Atomics may be performed using special instructions or Kernel-compiler cooperation
==== Memory Barriers ====
'''Memory Barriers''' ensure that memory accesses are sequenced so that multiple threads, processes, cores, or IO devices see a predictable view of memory.
* Leif Lindholm provides an excellent explanation of memory barriers.
** Blog series - I recommend this series, especially the introduction, as a very clear explanation of memory barrier issues.
*** Part 1 - [http://community.arm.com/groups/processors/blog/2011/03/22/memory-access-ordering--an-introduction Memory Access Ordering - An Introduction]
*** Part 2 - [http://community.arm.com/groups/processors/blog/2011/04/11/memory-access-ordering-part-2--barriers-and-the-linux-kernel Memory Access Ordering Part 2 - Barriers and the Linux Kernel]
*** Part 3 - [http://community.arm.com/groups/processors/blog/2011/10/19/memory-access-ordering-part-3--memory-access-ordering-in-the-arm-architecture Memory Access Ordering Part 3 - Memory Access Ordering in the ARM Architecture]
** Presentation at Embedded Linux Conference 2010 (Note: Acquire/Release in C++11 and ARMv8 aarch64 appeared after this presentation):
*** [http://elinux.org/images/f/fa/Software_implications_memory_systems.pdf Slides]
*** [http://free-electrons.com/pub/video/2010/elce/elce2010-lindholm-memory-450p.webm Video]
* [http://www.rdrop.com/users/paulmck/scalability/paper/whymb.2010.07.23a.pdf Memory Barriers - A Hardware View for Software Hackers] - This is a highly-rated paper that explains memory barrier issues - as the title suggests, it is designed to describe the hardware origin of the problem to software developers. Despite the fact that it is an introduction to the topic, it is still very technical.
* [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka14041.html ARM Technical Support Knowlege Article - In what situations might I need to insert memory barrier instructions?] - Note that there are some additional mechanisms present in ARMv8 aarch64, including Acquire/Release.
* [https://www.kernel.org/doc/Documentation/memory-barriers.txt Kernel Documentation on Memory Barriers] - discusses the memory barrier issue generally, and the solutions used within the Linux kernel. This is part of the kernel documentation.
* Acquire-Release mechanisms
** [http://blogs.msdn.com/b/oldnewthing/archive/2008/10/03/8969397.aspx MSDN Blog Post] with a very clear explanation of Acquire-Release.
** [http://preshing.com/20130922/acquire-and-release-fences/ Preshing on Programming post] with a good explanation.
** [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.genc010197a/index.html ARMv8 Instruction Set Architecture Manual] (ARM InfoCentre registration required) - See the section on Acquire/Release and Load/Store, especially Load/Store Exclusive (e.g., LDREX)
==== The Future of Memory ====
* NUMA (on steroids!)
* Non-volatile, byte-addressed main memory
* Non-local memory / Memory-area networks
* Memory encryption
==== Building Software ====
* Configuration Systems
** make-based systems
*** [https://www.gnu.org/software/automake/manual/html_node/index.html#Top The GNU Build System: autotools, autoconf, automake]
*** Configuration name ("triplet") -- ''cpu-manufacturer-operatingSystem'' or ''cpu-manufacturer-kernel-operatingSystem''
**** config.guess and config.sub
*** CMake
*** qmake
*** Meson
*** iMake and Others
** Non-make-based systems
*** Apache Ant
*** Apache Maven
*** Qt Build System
* Building in the Source Tree vs. Building in a Parallel Tree
** Pros and Cons
** [https://www.gnu.org/software/automake/manual/html_node/VPATH-Builds.html#VPATH-Builds GNU automake ''vpath'' builds]
* Installing and Testing in non-system directories
** Configuring installation to a non-standard directory
*** Running <code>configure</code> with <code>--prefix</code>
*** Running <code>make install</code> as a non-root user
*** DESTDIR variable for <code>make install</code>
** Runtime environment variables:
*** PATH
*** LD_LIBRARY_PATH and LD_PRELOAD (see the [http://man7.org/linux/man-pages/man8/ld.so.8.html ld.so manpage])
** Security when running software
*** Device access
**** Opening a TCP/IP or UDP/IP port below 1024
**** Accessing a <code>/dev</code> device entry
***** Root permission
***** Group permission
*** SELinux Type Enforcement
**** Enforcement mode
***** View enforcement mode: <code>getenforce</code>
***** Set enforcement mode: <code>setenforce</code>
**** Changing policy
***** [https://fedoraproject.org/wiki/SELinux/audit2why audit2why]
***** [https://fedoraproject.org/wiki/SELinux/audit2why audit2allow]
=== Week 9: Class II ===
* Portability Issues
=== Week 9 Deliverables ===
* Blog about your project
== Week 10 ==
=== Week 10: Class I ===
* Project hacking and discussion
=== Week 10 Deliverables ===
* Blog about your project.
* Note: March blogs are due Monday, April 2. Remember that the target is 1-2 posts/week, which is 4-8 posts/month.
== Week 11 ==
=== Week 11 - Class I ===
* Project hacking and discussion
=== Week 11 - Class II ===
* [[Compiler Intrinsics]]
* Project discussion
== Week 12 ==
=== Week 12 - Class I ===
* Class cancelled
=== Week 12 - Class II ===
* Project hacking and discussion
-->
<!--
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
== Week 6 ==
=== Week 6 - Class II ===
* [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab]] (Lab 6)
== Week 7 ==
=== Week 7 - Class I ===
Project discussion
=== Week 7 - Class II ===
Profiling
=== Week 7 Deliverables ===
Blog about your project.
=== Week 6 Deliverables ===
* Blog your results for the [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab]] (Lab 6) -- be sure to include links to your code, detailed results, and your reflection on the lab.
== Week x8 ==
=== Week x8 - Class I ===
* Review
* Plans for Remainder of Term
=== Week x8 - Class II ===
* [[Inline Assembly Language]]
* [[SPO600 Inline Assembler Lab|Inline Assembler Lab]] (Lab 7)
=== Week x8 Deliverables ===
* Blog about your Lab 7 results
== Week x9 ==
=== Week x9 - Class I ===
* Benchmarking and Profiling
** Notes to follow
=== Week x9 - Class II ===
* [[Fall 2017 SPO600 Project]]
=== Week x9 Deliverables ===
* Start blogging about your project!
###################################################################################
=== Week 2 - Class II ===
* [[SPO600 Assembler Lab|Assembly language lab]] (lab 3)
=== Week 2 Deliverables ===
* Blog your conclusion to the [[SPO600 Code Review Lab|Code Review Lab]] (Lab 1)
== Week 3 ==
=== Week 3 - Class I ===
* Continue group work on [[SPO600 Assembler Lab|Lab 3]].
=== Week 3 - Class II ===
* [[SPO600 Compiled C Lab]] (Lab 4)
=== Week 3 Deliverables ===
* Blog your conclusion to:
** [[SPO600 Assembler Lab|Lab 3]]
** [[SPO600 Compiled C Lab|Lab 4]]
== Week 4 ==
=== Week 4 - Class I ===
Software Optimization
* [[Compiler Optimizations]]
* [[Profile Guided Optimization]]
* Algorithm Selection
=== Week 4 - Class II ===
* [[SPO600 Algorithm Selection Lab]] (Lab 5)
=== Week 4 Deliverables ===
* Blog about your Lab 5 results.
== Week 5 ==
=== Week 5 - Class I ===
* Finish the [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab]]
=== Week 5 - Class II ===
* Introduction to Vector Processing/SIMD
* [[SPO600 Vectorization Lab|Vectorization Lab]] (Lab 6)
=== Week 5 Deliverables ===
* Blog your results for the [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab]] (Lab 5)
* Blog your results for the [[SPO600 Vectorization Lab|Vectorization Lab]] (Lab 6)
* For each of the above, be sure to include links to your code, detailed results, and your reflection on the lab.
== Week 6 ==
=== Week 6 - Class I ===
* [[Inline Assembly Language]] -- often used for:
*# Implementing a memory barrier
*# Performing an [[Atomic Operation]]
*#* '''Atomics''' are operations which must be completed in a single step (or appear to be completed in a single step) without potential interruption.
*#* Wikipedia has a good basic overview of the need for atomicity in the article on [http://en.wikipedia.org/wiki/Linearizability Linerarizability]
*# Gaining performance (by accessing processor features not exposed by the high-level language being used (C, C++, ...))
* [[SPO600 Inline Assembler Lab|Inline Assembler Lab]] (Lab 7)
=== Week 6 - Class II ===
* [[SPO600 Inline Assembler Lab|Inline Assembler Lab]] (Lab 7) continued...
=== Week 6 Deliverables ===
* Blog your Lab 7 results.
== Week 7 ==
=== Week 7 - Class I ===
==== Overview/Review of Processor Operation ====
* Fetch-decode-dispatch-execute cycle
* Pipelining
* Branch Prediction
* In-order vs. Out-of-order execution
** Micro-ops
==== Memory Basics ====
* Organization of Memory
** System organization
** Process organization
*** Text, data
*** Stack
*** Heap
* Memory Speeds
* Cache
** Cache lookup
** Cache synchronization and invalidation
** Cache line size
* Prefetch
** Prefetch hinting
==== Memory Architecture ====
* Virtual Memory and Memory Management Units (MMUs)
** General principles of VM and operation of MMUs
** Memory protection
*** Unmapped Regions
*** Write Protection
*** Execute Protection
*** Privilege Levels
** Swapping
** Text sharing
** Data sharing
** Shared memory for Inter-Process Communication
** Copy-on-Write (CoW)
** Demand Loading
** Memory mapped files
==== Memory Barriers ====
'''Memory Barriers''' ensure that memory accesses are sequenced so that multiple threads, processes, cores, or IO devices see a predictable view of memory.
* Leif Lindholm provides an excellent explanation of memory barriers.
** Blog series - I recommend this series, especially the introduction, as a very clear explanation of memory barrier issues.
*** Part 1 - [http://community.arm.com/groups/processors/blog/2011/03/22/memory-access-ordering--an-introduction Memory Access Ordering - An Introduction]
*** Part 2 - [http://community.arm.com/groups/processors/blog/2011/04/11/memory-access-ordering-part-2--barriers-and-the-linux-kernel Memory Access Ordering Part 2 - Barriers and the Linux Kernel]
*** Part 3 - [http://community.arm.com/groups/processors/blog/2011/10/19/memory-access-ordering-part-3--memory-access-ordering-in-the-arm-architecture Memory Access Ordering Part 3 - Memory Access Ordering in the ARM Architecture]
** Presentation at Embedded Linux Conference 2010 (Note: Acquire/Release in C++11 and ARMv8 aarch64 appeared after this presentation):
*** [http://elinux.org/images/f/fa/Software_implications_memory_systems.pdf Slides]
*** [http://free-electrons.com/pub/video/2010/elce/elce2010-lindholm-memory-450p.webm Video]
* [http://www.rdrop.com/users/paulmck/scalability/paper/whymb.2010.07.23a.pdf Memory Barriers - A Hardware View for Software Hackers] - This is a highly-rated paper that explains memory barrier issues - as the title suggests, it is designed to describe the hardware origin of the problem to software developers. Despite the fact that it is an introduction to the topic, it is still very technical.
* [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka14041.html ARM Technical Support Knowlege Article - In what situations might I need to insert memory barrier instructions?] - Note that there are some additional mechanisms present in ARMv8 aarch64, including Acquire/Release.
* [https://www.kernel.org/doc/Documentation/memory-barriers.txt Kernel Documentation on Memory Barriers] - discusses the memory barrier issue generally, and the solutions used within the Linux kernel. This is part of the kernel documentation.
* Acquire-Release mechanisms
** [http://blogs.msdn.com/b/oldnewthing/archive/2008/10/03/8969397.aspx MSDN Blog Post] with a very clear explanation of Acquire-Release.
** [http://preshing.com/20130922/acquire-and-release-fences/ Preshing on Programming post] with a good explanation.
** [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.genc010197a/index.html ARMv8 Instruction Set Architecture Manual] (ARM InfoCentre registration required) - See the section on Acquire/Release and Load/Store, especially Load/Store Exclusive (e.g., LDREX)
==== The Future of Memory ====
* NUMA (on steroids!)
* Non-volatile, byte-addressed main memory
* Non-local memory
* Memory encryption
=== Week 7 - Class II ===
* [[Winter 2017 SPO600 Project|Course Project]]
=== Week 7 Deliverables ===
* Blog your Lab 7 results, including the second part
* (To be announced: Project Deliverables)
== Week 8 ==
=== Week 8 - Class I ===
* Project Discussions
=== Week 8 - Class II ===
* Project Presentation #0
** Selected glibc function(s)
** Plan of Action
=== Week 8 Deliverables ===
* Blog about your selected function(s) and project plan
** Remember: You should be posting 1-2 times per week
#################################################################################
#################################################################################
#################################################################################
== Week 3 ==
=== Tuesday (Jan 26) ===
* Continue work on the [[SPO600 Assembler Lab|Assembly language lab]] (lab 3)
=== Friday (Jan 29) ===
* [[SPO600 Compiled C Lab|Compiled C lab]] (lab 4)
=== Week 3 Deliverables ===
* Blog about your [[SPO600 Assembler Lab|Assembly language lab]] (lab 3).
* Blog about your [[SPO600 Compiled C Lab|Compiled C lab]] (lab 4) experience and results. Consider the optimizations and transformations that the compiler performed.
* Remember that these posts (as all of your blog posts) will be marked both for communication (clarity, quality of writing (including grammar and spelling), formatting, use of links, completeness) and for content (lab completion and results). Your posts should contain both factual results as well as your reflections on the meaning of those results, the experience of performing the lab, and what you have learned.
'''Reminder:''' Blogs will be marked as they stand at the end of the month (Sunday).
== Week 4 ==
=== Tuesday (Feb 2) ===
Software Optimization
* [[Compiler Optimizations]]
* Algorithm Selection
=== Friday (Feb 5) ===
* [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab]] (Lab 6)
=== Week 4 Deliverables ===
* Blog about your Lab 5 results.
== Week 5 ==
=== Tuesday (Feb 9) ===
* Finish the [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab]]
* Discussion of Benchmarking Challenges
* Introduction to Vector Processing/SIMD
=== Friday (Feb 12) ===
* [[SPO600 Vectorization Lab|Vectorization Lab]] (Lab 6)
=== Week 5 Deliverables ===
* Blog your results for the [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab]] (Lab 5)
* Blog your results for the [[SPO600 Vectorization Lab|Vectorization Lab]] (Lab 6)
* For each of the above, be sure to include links to your code, detailed results, and your reflection on the lab.
== Week 6 ==
=== Tuesday (Feb 16) ===
* Discussion of Memory Architecture
=== Friday (Feb 19) ===
* [[Inline Assembly Language]] -- often used for:
*# Implementing a memory barrier
*# Performing an [[Atomic Operation]]
*# Gaining performance (by accessing processor features not exposed by the high-level language being used (C, C++, ...))
* [[SPO600 Inline Assembler Lab|Inline Assembler Lab]] (Lab 7)
=== Week 6 Deliverables ===
* Blog your Lab 7 results.
== Week 7 ==
=== Tuesday (Feb 23) ===
* Discussion of [[Winter 2016 SPO600 Compiler Options Presentation|Course Presentation]] assignment
=== Friday (Feb 26) ===
* Discussion of the [[Winter 2016 SPO600 Project|Course Project]]
=== Week 7 Deliverables ===
* Blog about your selected Presentation and Project topics.
== Week 8 ==
[http://connect.linaro.org/bkk16/|Linaro Connect] - No classes.
=== Week 8 Deliverables ===
* Prepare for your Presentation
* Work on your Project
* Blog about what you're doing!
== Week 9 ==
=== Tuesday (Mar 14) ===
* [[Winter 2016 SPO600 Compiler Options Presentation|Presentations]]
=== Friday (Mar 18) ===
* [[Winter 2016 SPO600 Compiler Options Presentation|Presentations]]
=== Week 9 Deliverables ===
* Blog about your Presentation, incorporating any discussion or feedback during the presentation.
== Week 10 ==
=== Tuesday (Mar 22) ===
* [[Winter 2016 SPO600 Project|Course Project]] - Stage I Updates
=== Week 10 Deliverables ===
* Blog your Stage I Updates. '''Important!''' - this will be used to assign your Stage I project mark! Include:
** Which software package you are working on
** Your experience building the software "out of the box" on x86_64 and AArch64 platforms
** Baseline results (performance)
** Which area of the software you will be working on and which approach you are going to take to optimizing the software...
**# Improving the Build Instructions (e.g., compiler options), OR
**# Changing the Software (substituting a different algorithm, or refactoring for better compiler optimization e.g., auto-vectorization), OR
**# Adding Platform-Specific code for AArch64
== Week 11 ==
=== Tuesday (Mar 29) ===
* Discussion & Hack Session
=== Thursday (Mar 31) ===
Reminder: '''Special Event:''' [https://www.eventbrite.ca/e/leadership-lunch-with-mike-shaver-engineer-director-for-facebook-tickets-23046621064 Leadership Lunch with Mike Shaver]
=== Friday (Apr 1) ===
* Discussion & Hack Session
=== Week 11 Deliverables ===
* Blog about your project work.
== Week 12 ==
=== Tuesday (Apr 5) ===
* Discussion & Hack Session
=== Friday (Apr 8) ===
* Project Stage II Updates
=== Week 12 Deliverables ===
* Blog your Stage II Project Updates by '''Midnight, Sunday, Apr 10.''' Note that this will be used for your Stage II project mark (20%).
== Week 13 ==
=== Tuesday (Apr 12) ===
* Wrap-Up Discussion
=== Friday (Apr 15) ===
* Stage III Project Updates
=== Week 13 Deliverables ===
* Blog your Stage III Project Updates by Midnight on Thursday, April 21.
* Complete ALL your blogging for this course by Midnight on Thursday, April 21. Make sure that you have included all of the labs, your presentation, and your project work. Remember that there should be at least 1-2 posts per week. Your blogging from April 1-April 21 will be used for your April communication mark.
== Week 2 ==
=== Tuesday (Sep 15) ===
{{Admon/tip|Bring Your Laptop|Classes are held in a [[Active Learning Classroom]]. If you have a laptop or other device with a VGA or HDMI output (such as a smartphone!) please bring it. You'll need either a local linux environment or an [[SSH]] client -- which is built-in to Linux, Mac, and Chromebook systems, and readily available for Windows, Android, and iOS devices.}}
* [[SPO600 Compiled C Lab|Compiled C Lab (Lab 2)]]
* Sheets from Last Week
** Open Source Student Agreement
=== Friday (Sep 18) ===
* Introductions
* [[Compiler Optimizations]]
* Introduction to the [[Fall 2015 SPO600 Compiler Options Presentation|Compiler Options Presentation]]
=== Week 2 Deliverables ===
* Blog about your [[SPO600 Code Review Lab|Code Review Lab (Lab 1)]] and [[SPO600 Compiled C Lab|Lab 2]] experience and results. For lab 2, consider the optimizations and transformations that the compiler performed. Remember that these posts (as all of your blog posts) will be marked both for communication (clarity, quality of writing (including grammar and spelling), formatting, use of links, completeness) and for content (lab completion and results). Your posts should contain both factual results as well as your reflections on the meaning of those results, the experience of performing the lab, and what you have learned.
== Week 3 ==
This week [[User:Chris Tyler|your professor]] is at [http://connect.linaro.org/sfo15/ Linaro Connect], an engineering conference run by [http://www.linaro.org Linaro] - a distributed not-for-profit collaborative technology company focused on Linux on ARM.
* [[Fall 2015 SPO600 Compiler Options Presentation|Select and prepare to teach the class about two compiler options]].
=== Week 3 Deliverables ===
* Be prepared to give your [[Fall 2015 SPO600 Compiler Options Presentation|presentation]] on Tuesday of next week (September 29).
== Week 4 ==
=== Tuesday (Sep 29) ===
* Presentations
=== Friday (Oct 2) ===
* Presentations
* Introduction to ARM64 hardware
* [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab (Lab 3)]]
=== Week 4 Deliverables ===
* Blog your [[Fall 2015 SPO600 Compiler Options Presentation|presentation]], incorporating any feedback and Q&A input that was given during/after the presentation in class.
== Week 5 ==
=== Tuesday (Oct 6) ===
* Class discussion/hacking on [[SPO600 Algorithm Selection Lab|Lab 3]].
=== Friday (Oct 9) ===
* More on Lab 3
* Discussion of Benchmarking
=== Week 5 Deliverables ===
* Blog your [[SPO600 Algorithm Selection Lab|Lab 3]] results.
== Week 6 ==
=== Tuesday (Oct 13) ===
* Discussion of benchmarking
** Control of variables
*** Competition for system resources
*** Repeatability
* Planning for a Compiler Options Test Framework
=== Friday (Oct 16) ===
* Compiler Options Framework
** Divide up tasks
** Start development
=== Week 6 Deliverables ===
* Blog your recommendations for the test framework design.
== Week 7 ==
=== Tuesday (Oct 20) ===
* Build the [[SPO600 Framework Project|Compiler Options Test Framework]]
=== Friday (Oct 23) ===
* Project selection
** Your task over reading week: Become an expert in building your selected software, and then make it work with the [[SPO600 Framework Project|Compiler Options Test Framework]]
=== Week 7 Deliverables ===
* Blog about the compiler options framework, and your work on that project.
* Blog about your selected project.
== Week 8 ==
=== Tuesday (Nov 3) ===
* No class scheduled - your [[User:Chris Tyler|prof]] is in Whitehorse, YK at an NSERC workshop.
* Please work on your [[Fall 2015 SPO600 Course Project|project]], and be ready to present on Friday.
=== Friday (Nov 6) ===
* Present your Stage I results for your [[Fall 2015 SPO600 Course Project|project]].
=== Week 8 Deliverables ===
* Blog about your [[Fall 2015 SPO600 Course Project|stage I project results]]. This will be used to assign the first marks for your project.
== Week 9 ==
=== Tuesday (Nov 10) ===
* [[Computer Architecture]] overview (see also the [[:Category:Computer Architecture|Computer Architecture Category]])
=== Friday (Nov 13) ===
* [[SPO600 Assembler Lab|Assembly language lab]] (lab 4)
=== Week 9 Deliverables ===
* Blog about your project progress (2+ posts per week).
* Blog the [[SPO600 Assembler Lab|Assembly language lab]] -- include your results, a link to your source code, and your reflections on the experience.
== Week 10 ==
=== Tuesday (Nov 17) ===
* Discussion & Hack Session
** [[SPO600 Assembler Lab|Assembly language lab (Lab 4) results]]
** Testing Framework
=== Friday (Nov 20) ===
* Hack session on the Testing Framework
=== Week 10 Deliverables ===
* Blog about your project work
* Blog about your Lab 5 results
== Week 11 ==
=== Tuesday (Nov 22) ===
* SIMD and Vectorization
* [[SPO600 Vectorization Lab|Vectorization Lab (Lab 6)]]
=== Friday (Nov 25) ===
* Discussion of the State of the Framework
* Hack Session
=== Week 11 Deliverables ===
* Blog your [[SPO600 Vectorization Lab|Lab 6]] results.
== Week 12 ==
=== Tuesday (Dec 1) ===
* Stage II Results - Brief Presentations
=== Friday (Dec 4) ===
* '''No Class''' - Early start to Exam Week
=== Week 12 Deliverables ===
* Blog about your Project Status - Stage II Results
** Provide results for the various flag combinations you tested
** Discuss the results, highlighting any anomalies
== Final Deliverables ==
* Blog about your Project Status - Stage III Results
** Important: Incorporate any feedback on your Stage II results
** Outline what you learned from your investigation into various combination of GCC flags
** Discuss what the upstream projects should do based on these results
** Communicate the results to the upstream project, if appropriate
** Outline further investigation that should be undertaken
* Blog a reflective blog post on the course
** What you have learned
** What you already knew
** What was good or bad about the way the course proceeded]
** How you might use this knowledge in the future
* This is the last chance to submit any lab postings, etc.
'''All blog postings must be in by Friday, December 18, at 11:59 pm to be included in the final grade.'''
-->
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This is the schedule and main index page for the [[SPO600]] ''Software Portability and Optimization'' course for Winter 2020.
<!-- {{Admon/important|It's Alive!|This [[SPO600]] weekly schedule will be updated as the course proceeds - dates and content are subject to change. The cells in the summary table will be linked to relevant resources and labs as the course progresses.}} -->
{{Admon/important|Content being Updated|This page is in the process of being updated from a previous semester's content. It is not yet updated for the current semester. Do not rely on the accuracy of this information until this warning is removed.}}
<!-- {{Admon/obsolete|[[Current SPO600 Weekly Schedule]]}} -->
== Schedule Summary Table ==
This is a summary/index table. Please follow the links in each cell for additional detail which will be added below as the course proceeds -- especially for the ''Deliverables'' column.
{|cellspacing="0" width="100%" cellpadding="5" border="1" style="background: #e0e0ff"
|-
!Week!!Week of...!!width="28%"|Class I<br/>Tuesday 1:30-3:15<br />Room B1024!!width="28%"|Class II<br/>Friday 11:40-1:25<br />Room K1263!!width="28%"|Deliverables<br/>(Summary - click for details)
|-
|1||Jan 06||[[#Week 1 - Class I|Introduction to the Course / Introduction to the Problem / How is code accepted into an open source project? (Homework: Lab 1)]]||[[#Week 1 - Class II|Computer architecture basics / Binary Representation of Data / Introduction to Assembly Language]]||[[#Week 1 Deliverables|Set up for the course]]
|-
|2||Jan 13||[[#Week 2 - Class I|6502 Assembly Basics Lab (Lab 2)]]||[[#Week 2 - Class II|Assembly language conventions and Examples / Project Selection]]||[[#Week 2 Deliverables|Lab 1 and 2]]
|-
|3||Jan 20||[[#Week 3 - Class I|6502 Strings and Memory Lab (Lab 3)]]||[[#Week 3 - Class II|Computer math / Building Code]]||[[#Week 3 Deliverables|Lab 3, Selected Project]]
|-
|4||Jan 27||[[#Week 4 - Class I|6502 Math Lab (Lab 4)]]||[[#Week 4 - Class II|System routines / Sysadmin for Devs]]||[[#Week 4 Deliverables|Lab 4, Project Build]]
|-
|5||Feb 03||[[#Week 5 - Class I|6502 Application Lab (Lab 5)]]||[[#Week 5 - Class II|Introduction to x86_64 and AArch64 architectures]]||[[#Week 5 Deliverables|Lab 5]]
|-
|6||Feb 10||[[#Week 6 - Class I|64-bit Assembly Language Lab (Lab 6)]]||[[#Week 6 - Class II|Profiling]]||[[#Week 6 Deliverables|Lab 6]]
|-
|7||Feb 17||[[#Week 7 - Class I|Profiling Lab (Lab 7)]]||[[#Week 7 - Class II|Project Stage 1]]||[[#Week 7 Deliverables|Lab 7, Project Profiling]]
|-
|Reading||Feb 24||style="background: #f0f0ff" colspan="5" align="center"|Reading Week
|-
|8||Mar 02||[[#Week 8 - Class I|Algorithm Selection Lab (Lab 8)]]||[[#Week 8 - Class II|SIMD and Vectorization]]||[[#Week 8 Deliverables|Project Stage 1 due]]
|-
|9||Mar 09||[[#Week 9 - Class I|SIMD Lab (Lab 9)]]||[[#Week 9 - Class II|Identifying Optimization Opportunities]]||[[#Week 9 Deliverables|Lab 9]]
|-
|10||Mar 16||[[#Week 10 - Class I|Atomics]]||[[#Week 10 - Class II|Project Discussion]]||[[#Week 10 Deliverables|Project Work]]
|-
|11||Mar 23||[[#Week 11 - Class I|Project Hacking]]||[[#Week 11 - Class II|Memory Ordering, Synchronization, and Barriers]]||[[#Week 11 Deliverables|Project Stage 2 due]]
|-
|12||Mar 30||[[#Week 12 - Class I|ifunc]]||[[#Week 12 - Class II|Emerging directions in system architecture]]||[[#Week 12 Deliverables|Project Work]]
|-
|13||Apr 06||[[#Week 13 - Class I|Demos]]||[[#Week 13 - Class II|Course wrap-up discussion]]||[[#Week 13 Deliverables|Project Stage 3 due]]
|-
|}
== Week 1 ==
=== Week 1 - Class I ===
==== Introduction to the Problems ====
===== Porting and Portability =====
* Most software is written in a '''high-level language''' which can be compiled into [[Machine Language|machine code]] for a specific computer architecture. In many cases, this code can be compiled for multiple architectures. However, there is a lot of existing code that contains some architecture-specific code fragments written in architecture-specific high-level code or in [[Assembly Language]].
* Reasons that code is architecture-specific:
** System assumptions that don't hold true on other platforms
*** Variable or [[Word|word]] size
*** [[Endian|Endianness]]
** Code that takes advantage of platform-specific features
* Reasons for writing code in Assembly Langauge include:
** Performance
** [[Atomic Operation|Atomic Operations]]
** Direct access to hardware features, e.g., CPUID registers
* Most of the historical reasons for including assembler are no longer valid. Modern compilers can out-perform most hand-optimized assembly code, atomic operations can be handled by libraries or [[Compiler Intrinsics|compiler intrinsics]], and most hardware access should be performed through the operating system or appropriate libraries.
* A new architecture has appeared: AArch64, which is part of [http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php ARMv8]. This is the first new [[Computer Architecture|computer architecture]] to appear in several years (at least, the first mainstream computer architecture).
* At this point, most key open source software (the software typically present in a Linux distribution such as Ubuntu or Fedora, for example) now runs on AArch64. However, it may not run as well as on older architectures (such as x86_64).
===== Benchmarking and Profiling =====
Benchmarking involves testing software performance under controlled conditions so that the performance can be compared to other software, the same software operating on other types of computers, or so that the impact of a change to the software can be gauged.
Profiling is the process of analyzing software performance on finer scale, determining resource usage per program part (typically per function/method). This can identify software bottlenecks and potential targets for optimization.
===== Optimization =====
Optimization is the process of evaluating different ways that software can be written or built and selecting the option that has the best performance tradeoffs.
Optimization may involve substituting software algorithms, altering the sequence of operations, using architecture-specific code, or altering the build process. It is important to ensure that the optimized software produces correct results and does not cause an unacceptable performance regression for other use-cases, system configurations, operating systems, or architectures.
The definition of "performance" varies according to the target system and the operating goals. For example, in some contexts, low memory or storage usage is important; in other cases, fast operation; and in other cases, low CPU utilization or long battery life may be the most important factor. It is often possible to trade off performance in one area for another; using a lookup table, for example, can reduce CPU utilization and improve battery life in some algorithms, in return for increased memory consumption.
Most advanced compilers perform some level of optimization, and the options selected for compilation can have a significant effect on the trade-offs made by the compiler, affecting memory usage, execution speed, executable size, power consumption, and debuggability.
===== Build Process =====
Building software is a complex task that many developers gloss over. The simple act of compiling a program invokes a process with five or more stages, including pre-proccessing, compiling, optimizing, assembling, and linking. However, a complex software system will have hundreds or even thousands of source files, as well as dozens or hundreds of build configuration options, auto configuration scripts (cmake, autotools), build scripts (such as Makefiles) to coordinate the process, test suites, and more.
The build process varies significantly between software packages. Most software distribution projects (including Linux distributions such as Ubuntu and Fedora) use a packaging system that further wraps the build process in a standardized script format, so that different software packages can be built using a consistent process.
In order to get consistent and comparable benchmark results, you need to ensure that the software is being built in a consistent way. Altering the build process is one way of optimizing software.
Note that the build time for a complex package can range up to hours or even days!
==== General Course Information ====
* Course resources are linked from the CDOT wiki, starting at https://wiki.cdot.senecacollege.ca/wiki/SPO600 (Quick find: This page will usually be Google's top result for a search on "SPO600").
* Coursework is submitted by blogging.
* Quizzes will be short (1 page) and will be held without announcement at any time, generally at the start of class. There is no opportunity to re-take a missed quiz, but your lowest three quiz scores will not be counted, so do not worry if you miss one or two.
** Students with test accommodations: an alternate monthly quiz is available in the Test Centre. See the professor for details.
* Course marks (see Weekly Schedule for dates):
** 60% - Project Deliverables
** 20% - Communication (Blog and Wiki writing)
** 20% - Labs and Quizzes (10% labs - completed/not completed; 10% for quizzes - lowest 3 scores not counted)
* Classes will be held in an [[Active Learning Classroom]] -- you are encouraged to bring your own laptop to class. If you do not have a laptop, consider signing one out of the Learning Commons for class, or using a smartphone with an HDMI adapter.
* For more course information, refer to the SPO600 Weekly Schedule (this page), the [http://www.senecacollege.ca/ssos/findWithoutSemester/spo600/sict Course Outline], and [[SPO600 Course Policies]].
==== Course and Setup: Accounts, agreements, servers, and more ====
* [[SPO600 Communication Tools]]
* [[Fall 2019 SPO600 Participants]] page
* [[SPO600_Servers#Preparatory_Steps|Key generation]] for [[SSH]] to the [[SPO600 Servers]].
==== How open source communities work ====
* Do the [[SPO600 Code Review Lab|Code Review Lab (Lab 1)]] as homework.
=== Week 1 - Class II ===
* Compiler Operation
** Stages of Compilation
**# Preprocessing
**# Compiling
**# Assembling
**# Linking
* Analyzing compiler output
** Disassembly
* [[SPO600 Compiled C Lab|Compiled C Lab]] (Lab 2)
=== Week 1 Deliverables ===
# Course setup:
## Set up your [[SPO600 Communication Tools]] - in particular, set up a blog and add it to [http://zenit.senecac.on.ca/~chris.tyler/planet/ Planet CDOT] (via the [[Planet CDOT Feed List]]).
## Add yourself to the [[Current SPO600 Participants]] page (leave the projects columns blank).
## Generate a [[SPO600_Servers#Preparatory_Steps|pair of keys]] for [[SSH]] and email the public key to your professor, so that he can set up your access to the [[SPO600 Servers|class servers]].
## Optional (strongly recommended): [[SPO600 Host Setup|Set up a personal Linux system]].
## Optional: Purchase an AArch64 development board (such as a [http://96boards.org 96Boards] HiKey or Raspberry Pi 3 or 4. (If you use a Pi, install a 64-bit Linux operating system on it, not a 32-bit version).
# Complete [[SPO600 Code Review Lab|Lab 1]] and write it up on your blog.
== Week 2 ==
=== Week 2 - Class I ===
* [[Make and Makefiles]]
* [[Assembly Language]]
* [[SPO600 Assembler Lab|Assembler Lab]] (Lab 3)
=== Week 2 - Class II ===
* [[SPO600 Assembler Lab|Assembler Lab]] (Lab 3)
=== Week 2 Deliverables ===
* Blog your results and conclusion to [[SPO600 Code Review Lab|Code Review Lab (Lab 1)]] and [[SPO600 Compiled C Lab|Compiled C Lab (Lab 2)]]
* Blog about your initial work on [[SPO600 Assembler Lab|Lab 3]].
* Set up your account on the [[SPO600_Communication_Tools#Slack|Seneca Open Source Slack Workspace]].
== Week 3 ==
=== Week 3 - Class I ===
* ''Sysadmin for Devs''
** In-class discussion of tips and tricks for efficient work on a Linux server
=== Week 3 - Class II ===
* Finish [[SPO600 Assembler Lab|Lab 3]]
=== Week 3 - Deliverables ===
* Finish and blog your detailed results for the [[SPO600 Assembler Lab|Assembler Lab]] (Lab 3)
== Week 4 ==
=== Week 4 - Class I ===
* Binary Representation of Data
** Integers
*** Integers are the basic building block of binary numbers.
*** In an unsigned integer, the bits are numbered from right to left starting at 0, and the value of each bit is <code>2<sup>bit</sup></code>. The value represented is the sum of each bit multiplied by its corresponding bit value. The range of an unsigned integer is <code>0:2<sup>bits</sup>-1</code> where bits is the number of bits in the unsigned integer.
*** Signed integers are generally stored in twos-complement format, where the highest bit is used as a sign bit. If that bit is set, the value represented is <code>-(!value)-1</code> where ! is the NOT operation (each bit gets flipped from 0→1 and 1→2)
** Fixed-point
*** A fixed-point value is encoded the same as an integer, except that some of the bits are fractional -- they're considered to be to the right of the "binary point" (binary version of "decimal point" - or more generically, the ''radix point''). For example, binary 000001.00 is decimal 1.0, and 000001.11 is decimal 1.75.
*** An alternative to fixed-point values is integer values in a smaller unit of measurement. For example, some accounting software may use integer values representing cents. For input and display purposes, dollar and cent values are converted to/from cent values.
** Floating-point
*** Floating point numbers have three parts: a ''sign bit'' (0 for positive, 1 for negative), a ''mantissa'' or ''significand'', and an ''exponent''. The value is interpreted as <code>''sign'' mantissa * 2<sup>exponent</sup></code>.
** Sound
** Graphics
** Compression techniques
*** Huffman encoding / Adaptive arithmetic encoding
*** Repeated sequence encoding (1D, 2D, 3D)
*** Decomposition
*** Pallettization
*** Psychoacoustic and psychovisual compression
* Problem: Scaling Sound
** Naive approach
** Lookup table
** Fixed-point multiply and shift
=== Week 4 - Class II ===
* [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab]] (Lab 4)
=== Week 4 Deliverables ===
* Blog your results to [[SPO600 Algorithm Selection Lab|Lab 4]]
== Week 5 ==
=== Week 5 - Class I ===
* SIMD
** SIMD is an acronym for "Single Instruction, Multiple Data", and refers to a class of instructions which perform the same operation on several separate pieces of data in parallel. SIMD instructions also include related instructions to set up data for SIMD processing, and to summarize results.
** SIMD is based on very wide registers (128 bits to 2048 bits on implementations current as of 2019), and these wide registers can be treated as multiple "lanes" of similar data. These SIMD registers, also called vector registers, can therefore be thought of as small arrays of values.
** A 128-bit SIMD register can be used as:
*** two 64-bit lanes
*** four 32-bit lanes
*** eight 16-bit lanes
*** sixteen 8-bit lanes
** Each architecture has a different notation for SIMD registers. In AArch64 (which will be our focus):
*** Vector usage uses the notation v''n''.''s'' where ''n'' is the register number and ''s'' is the shape of the lanes, expressed as the number of lanes and a letter indicating the width of the lanes: q for quad-word (128 bits), d for double-word (64 bits), s for single-word (32 bits), h for half-word (16 bits), and b for byte (8 bits). Therefore, <code>v0.16b</code> is vector register 0 used as 16 lanes of 8 bits (1 byte) each, while <code>v8.4s</code> is vector register 8 used as 4 lanes of 32 bits each. Most instructions permit either 64 or 128 bits of the register to be used.
*** Scalar usage uses the lane width letter followed by the vector register number. Therefore, <code>q3</code> refers to vector register 3 used as a single 128-bit value, and <code>s3</code> refers to the same register used as a single 32-bit register. Note that these are the same register referred to as v3 for vector usage. When using less than 128 bits, the remaining bits are either zero-filled (unsigned usage) or sign-extended (signed usage: the upper bits are filled with the sign bit, i.e., the same value as the high bit of the active part of the register).
** Most SIMD operations work on corresponding lanes of the operand registers. For example, the AArch64 instruction <code>add v0.8h, v1.8h, v2.8h</code> will take the value in the first lane of register 1, add the value in the first lane of register 2, and place the result in the first lane of register 0. At the same time, the other lanes are processed in the same way, resulting in 8 simultaneous addition operations being performed.
** A small number of SIMD operations work across lanes, e.g., to find the lowest or highest value in all of the lanes, to add the lanes together, or to duplicate a single value into all of the lanes of a register. These are usually used to set up or summarize the results of SIMD operations -- for example, a value of 0 might be duplicated into all of the lanes of a result register, then a loop applied to sum array data into the results register, and then a lane-summing operation performed to merge the results from all of the lanes.
* SIMD capabilities can be used in a program in one of three different ways:
*# The compiler's ''auto-vectorizer'' can be used to identify sections of code to which SIMD is applicable, and SIMD code will automatically be generated.
*#* This works for the basic SIMD operations, but may not be applicable to advanced SIMD instructions, which don't clearly map to C statements.
*#* The compiler will be very cautious about vectorizing code. See the Resources section below for insight into these challenges.
*#** In order to vectorize a loop, among other things, the number of loop iterations needs to be known before the loop starts, memory layout must meet SIMD alignment requirements, loops must not overlap in a way that is affected by vectorization.
*#** The compiler will also calculate a cost for the vectorization: in the case of a small loop, the extra setup before the loop and processing after the loop may negate the benefits of vectorization.
*#* Vectorization in applied by default only at the -O3 level in most compilers. In GCC:
*#** The main individual feature flag to turn on vectorization is <code>-ftree-vectorize</code> (enabled by default at -O3, disabled at other levels).
*#** You can see all of the vectorization decisions using <code>-fopt-info-vec-all</code> or you can see just the missed vectorizations using <code>-fopt-info-vec-missed</code> (which is usually what you want to focus on, because it show only the loops where vectorization was ''not'' enabled, and the reason that it was not). This approach is generally very portable.
*# We can explicitly include SIMD instructions in a C program by using [[Inline Assembly Language|Inline Assembler]]. This is obviously architecture-specific, so it is important to use C preprocessor directives to include/exclude this code depending on the platform for which it is compiled, and to use a generic C implementation on any platform for which you are not providing an inline assembler version.
*# ''C Intrinsics'' are function-like extensions to the C language. Although they look like functions, they are compiled inline, and they are used to provide access to features which are not provided by the C language itself. There is a group of intrinsics which provide access to SIMD instructions. However, the benefit of using these over inline assembler is debatable. SIMD intrinsics are not portable, and should be included with C preprocessor directives like inline assembler.
=== Week 5 - Class II ===
* [[SPO600 SIMD Lab]] (Lab 5)
=== Week 5 Resources ===
==== Auto-vectorization ====
* [https://gcc.gnu.org/projects/tree-ssa/vectorization.html Auto-Vectorization in GCC] - Main project page for the GCC auto-vectorizer.
* [http://locklessinc.com/articles/vectorize/ Auto-vectorization with gcc 4.7] - An excellent discussion of the capabilities and limitations of the GCC auto-vectorizer, intrinsics for providing hints to GCC, and other code pattern changes that can improve results. Note that there has been some improvement in the auto-vectorizer since this article was written. '''This article is strongly recommended.'''
* [https://software.intel.com/sites/default/files/8c/a9/CompilerAutovectorizationGuide.pdf Intel (Auto)Vectorization Tutorial] - this deals with the Intel compiler (ICC) but the general technical discussion is valid for other compilers such as gcc and llvm
==== Inline Assembly Language ====
* [[Inline Assembly Language]]
* [http://developer.arm.com ARM Developer Information Centre]
** [https://developer.arm.com/products/architecture/a-profile/docs/den0024/a ARM Cortex-A Series Programmer’s Guide for ARMv8-A]
* The ''short'' guide to the ARMv8 instruction set: [https://www.element14.com/community/servlet/JiveServlet/previewBody/41836-102-1-229511/ARM.Reference_Manual.pdf ARMv8 Instruction Set Overview] ("ARM ISA Overview")
* The ''long'' guide to the ARMv8 instruction set: [https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile] ("ARM ARM")
==== C Intrinsics - AArch64 SIMD ====
* [https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics ARM NEON Intrinsics Reference]
* [https://gcc.gnu.org/onlinedocs/gcc/ARM-C-Language-Extensions-_0028ACLE_0029.html GCC ARM C Language Extensions]
=== Week 5 Deliverables ===
* Blog about the SIMD Lab
== Week 6 ==
=== Week 6 - Class I ===
* [[Compiler Optimizations]]
* Advanced Compiler Optimizations
** [[Profile Guided Optimization]]
** [[Link Time Optimization]]
* [[Profiling]]
=== Week 6 - Class II ===
* Continue work on the [[SPO600 SIMD Lab|SIMD Lab]] (Lab 5)
=== Week 6 Deliverables ===
* Blog about your results to Lab 5
== Week 7 ==
=== Week 7 - Class I ===
Building software...
* Configuration Systems
** make-based systems
*** [https://www.gnu.org/software/automake/manual/html_node/index.html The GNU Build System: autotools, autoconf, automake]
**** GNU autotools makes extensive use of the ''configuration name'' ("triplet") -- ''cpu-manufacturer-operatingSystem'' or ''cpu-manufacturer-kernel-operatingSystem'' (e.g.,
**** config.guess and config.sub
*** CMake
*** qmake
*** Meson
*** iMake and Others
** Non-make-based systems
*** Apache Ant
*** Apache Maven
*** Qt Build System
* Building in the Source Tree vs. Building in a Parallel Tree
** Pros and Cons
** [https://www.gnu.org/software/automake/manual/html_node/VPATH-Builds.html#VPATH-Builds GNU automake ''vpath'' builds]
* Installing and Testing in non-system directories
** Configuring installation to a non-standard directory
*** Running <code>configure</code> with <code>--prefix</code>
*** Running <code>make install</code> as a non-root user
*** DESTDIR variable for <code>make install</code>
** Runtime environment variables:
*** PATH
*** LD_LIBRARY_PATH and LD_PRELOAD (see the [http://man7.org/linux/man-pages/man8/ld.so.8.html ld.so manpage])
** Security when running software
*** Device access
**** Opening a TCP/IP or UDP/IP port below 1024
**** Accessing a <code>/dev</code> device entry
***** Root permission
***** Group permission
*** SELinux Type Enforcement
**** Enforcement mode
***** View enforcement mode: <code>getenforce</code>
***** Set enforcement mode: <code>setenforce</code>
**** Changing policy
***** [https://fedoraproject.org/wiki/SELinux/audit2why audit2why]
***** [https://fedoraproject.org/wiki/SELinux/audit2why audit2allow]
* Build Dependencies
* Packaging
* General information about the SPO600 projects
** Goal
** Stages
** Approaching the Project
=== Week 7 - Class II ===
* [[Fall 2019 SPO600 Project|Project Selection]]
=== Week 7 Deliverables ===
* Catch up on any incomplete labs (and blog about them)
* Blog about your project selection progress
== Week 8 ==
=== Week 8 - Class I ===
==== Overview/Review of Processor Operation ====
* Fetch-decode-dispatch-execute cycle
* Pipelining
* Branch Prediction
* In-order vs. Out-of-order execution
** Micro-ops
==== Memory Basics ====
* Organization of Memory
** Process organization
*** Text, data
*** Stack
*** Heap
** System organization
*** Kernel memory in process maps
*** Use of unallocated memory for buffers and cache
* Memory Speeds
* Cache
** Cache lookup
** Cache synchronization and invalidation
** Cache line size
* Prefetch
** Prefetch hinting
==== Memory Architecture ====
* Virtual Memory and Memory Management Units (MMUs)
** General principles of Virtual Memory and operation of MMUs
** Memory protection
*** Unmapped Regions
*** Write Protection
*** Execute Protection
*** Privilege Levels
** Swapping
** Text sharing
** Demand Loading
** Data sharing
*** Shared memory for Inter-Process Communication
*** Copy-on-Write (CoW)
** Memory mapped files
==== Memory Statistics ====
* Resident Set Size (RSS) and Virtual Set Size (VSS)
* Total memory consumption per process
* Total system memory consumption
==== Software Impact ====
* Alignment checks
* Page boundary crossing
=== Week 8 - Class II ===
* Project Discussion
=== Week 8 Deliverables ===
* Blog about your project work
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== Week 2 ==
=== Week 2 - Class I ===
* Sysadmin for Developers
* Building Code
** [[Make and Makefiles]]
** [[SPO600 Code Building Lab|Code Building Lab]] (Lab 2)
=== Week 2 - Class II ===
* Compiler Operation
** Stages of Compilation
**# Preprocessing
**# Compiling
**# Assembling
**# Linking
* Analyzing compiler output
** Disassembly
* [[SPO600 Compiled C Lab|Compiled C Lab]] (Lab 3)
=== Week 2 Deliverables ===
* Blog your conclusion to the [[SPO600 Code Review Lab|Code Review Lab (Lab 1)]]
* Blog the results and conclusion from the [[SPO600 Code Building Lab|Compiled C Lab (Lab 2)]]
* Blog the results and conclusion from the [[SPO600 Compiled C Lab|Compiled C Lab (Lab 3)]]
== Week 3 ==
=== Week 3 - Class I ===
* [[Make and Makefiles]]
* [[Assembly Language]]
* [[SPO600 Assembler Lab|Assembler Lab]] (Lab 4)
=== Week 3 - Class II ===
* [[SPO600 Assembler Lab|Assembler Lab]] (Lab 4) Continued...
=== Week 3 Deliverables ===
* Blog about [[SPO600 Assembler Lab|Lab 4]].
== Week 4 ==
=== Week 4 - Class I ===
* [[SPO600 Assembler Lab|Assembler Lab]] (Lab 4) Wrap-up...
* Binary Representation of Data
** Integers
** Fixed-point
** Floating-point
** Sound
** Graphics
** Compression techniques
*** Huffman encoding / Adaptive arithmetic encoding
*** Repeated sequence encoding (1D, 2D, 3D)
*** Decomposition
*** Pallettization
*** Psychoacoustic and psychovisual compression
=== Week 4 - Class II ===
* [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab]] (Lab 5)
=== Week 4 Deliverables ===
* Blog your results to [[SPO600 Assembler Lab|Lab 4]]
== Week 5 ==
=== Week 5 - Class I ===
'''Note:''' Your prof is away!
* Investigate various tools available for [[Profiling]]
** Ensure that you know how to use <code>gprof</code>
** Ensure that you know how to use at least one other Linux profiling tool
** Blog about it, including the example of profiling the sound scaling programs from [[SPO600 Algorithm Selection Lab|Lab 5]]
=== Week 5 - Class II ===
* SIMD and Auto-vectorization
* [[Inline Assembly Language|Inline Assembler]]
* C Intrinsics
* [[SPO600 Vectorization Lab|Vectorization Lab]] (Optional lab - recommended)
=== Week 5 Deliverables ===
* Blog your Profiling investigation results
* Optional: Blog about the Vectorization Lab if you performed it
== Week 6 ==
=== Week 6 - Class I ===
* Thanksgiving -- enjoy time with your friends and family!
** No class
=== Week 6 - Class II ===
* '''Note: Your prof is away'''
** Room is available to collaborate if desired -- AV unlock code is 2598
* Perform the [[SPO600 Inline Assembler Lab|Inline Assembler Lab]] (Lab 6)
=== Week 6 Deliverables ===
* Blog your results to the [[SPO600 Inline Assembler Lab|Inline Assembler Lab]] (Lab 6)
== Week 7 ==
=== Week 7 - Class I ===
* Discussion
=== Week 7 - Class II ===
* Discussion
=== Week 7 Deliverables ===
* Wrap up any labs not yet completed.
== Week 8 ==
=== Week 8 - Class I ===
* [[Fall 2018 SPO600 Project]]
=== Week 8 - Class II ===
* Project Discussion
=== Week 8 Deliverables ===
* Blog about your project.
== Week 2 ==
=== Week 2 - Class I ===
* Binary Representation of Data
** Numbers
*** Integers
*** Fixed-point numbers
*** Floating-point numbers
** Characters
*** ASCII
*** ISO8859-1
*** Unicode
**** Encoding schemes
*** EBCDIC
** Images
** Sound
* [[Computer Architecture]] overview (see also the [[:Category:Computer Architecture|Computer Architecture Category]])
* A first look at the x86_64 and AArch64 Architectures and ISA
** Register file comparison
** Instruction encoding
** ELF
** Procedure calling conventions
==== Reference ====
* [[Computer Architecture]] and [[:Category:Computer Architecture|Computer Architecture Category]]
* [[Aarch64 Register and Instruction Quick Start]]
* [[x86_64 Register and Instruction Quick Start]]
=== Week 2 - Class II ===
* Compiler Operation
** Stages of Compilation
**# Preprocessing
**# Compiling
**# Assembling
**# Linking
* Analyzing compiler output
** Disassembly
* [[SPO600 Compiled C Lab|Compiled C Lab (Lab 2)]]
=== Week 2 Deliverables ===
* Blog your conclusion to the [[SPO600 Code Review Lab|Code Review Lab (Lab 1)]]
* Blog the results and conclusion from the [[SPO600 Compiled C Lab|Compiled C Lab (Lab 2)]]
== Week 3 ==
=== Week 3 - Class I ===
* [[Assembler Basics]]
* [[Syscalls]]
* [[SPO600 Assembler Lab|Assembler Lab (Lab 3)]].
=== Week 3 - Class II ===
* <strike>Complete Lab 3</strike> <span style="color: #ff0000">Class cancelled</span>
=== Week 3 Deliverables ===
* Blog your initial experience on the [[SPO600 Assembler Lab|Assembler Lab (Lab 3)]].
== Week 4 ==
=== Week 4 - Class I ===
* Continue work in class on the [[SPO600 Assembler Lab|Assembler Lab (Lab 3)]].
=== Week 4 - Class II ===
* Continue work in class on the [[SPO600 Assembler Lab|Assembler Lab (Lab 3)]].
=== Week 4 Deliverables ===
* Blog your [[Lab 3]] results.
== Week 5 ==
=== Week 5 - Class I ===
* [[Compiler Optimizations]]
=== Week 5 - Class II ===
* Advanced Compiler Optimizations
** [[Profile Guided Optimization]]
** [[Link Time Optimization]]
* Introduction to Vector Processing/SIMD
** [[SPO600 Vectorization Lab|Vectorization Lab]] (Lab 4) as homework
* [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab]] (Lab 5) in work groups
=== Week 5 Deliverables ===
* Blog your results for [[SPO600 Vectorization Lab|Lab 4]] and [[SPO600 Algorithm Selection Lab|Lab 5]] -- be sure to include links to your code, detailed results, and your reflection on the lab.
== Week 6 ==
=== Week 6 - Class I ===
* [[Inline Assembly Language]] -- often used for:
*# Implementing a memory barrier
*# Performing an [[Atomic Operation]]
*#* '''Atomics''' are operations which must be completed in a single step (or appear to be completed in a single step) without potential interruption.
*#* Wikipedia has a good basic overview of the need for atomicity in the article on [http://en.wikipedia.org/wiki/Linearizability Linearizability]
*# Gaining performance (by accessing processor features not exposed by the high-level language being used (C, C++, ...))
* [[SPO600 Inline Assembler Lab|Inline Assembler Lab]] (Lab 6)
=== Week 6 - Class II ===
* [[Addressing Mode|Processor Addressing Modes]]
* Navigating CPU technical documentation
* A (very) quick intro to GDB
* [[Winter 2018 SPO600 Project|Project]]: Selecting, Building, Benchmarking, and Profiling
=== Week 6 Deliverables ===
* Blog your Lab 5 and 6 results.
* Start blogging about your project.
* '''Reminder:''' Blogs will be marked as they stand at 11:59 on March 4, the Sunday at the end of Reading Week.
== Week 7 ==
=== Week 7 - Class I ===
* Project Discussion
=== Week 7 - Class II ===
* [[Profiling]]
=== Week 7 Deliverables ===
* Complete your [[Winter_2018_SPO600_Project#Stage_1|Stage I]] project posts on your blog.
== Week 8 ==
=== Week 8 - Class I ===
* Sysadmin for Developers
* Project Discussion
=== Week 8 - Class II ===
==== Overview/Review of Processor Operation ====
* Fetch-decode-dispatch-execute cycle
* Pipelining
* Branch Prediction
* In-order vs. Out-of-order execution
** Micro-ops
==== Memory Basics ====
* Organization of Memory
** Process organization
*** Text, data
*** Stack
*** Heap
** System organization
* Memory Speeds
* Cache
** Cache lookup
** Cache synchronization and invalidation
** Cache line size
* Prefetch
** Prefetch hinting
==== Memory Architecture ====
* Virtual Memory and Memory Management Units (MMUs)
** General principles of Virtual Memory and operation of MMUs
** Memory protection
*** Unmapped Regions
*** Write Protection
*** Execute Protection
*** Privilege Levels
** Swapping
** Text sharing
** Demand Loading
** Data sharing
*** Shared memory for Inter-Process Communication
*** Copy-on-Write (CoW)
** Memory mapped files
=== Software Impact ===
* Alignment checks
* Page boundary crossing
=== Week 8 Delivarables ===
* Blog about your project
== Week 9 ==
=== Week 9 - Class I ===
==== Atomics ====
* '''Atomics''' are operations which must be completed in a single step (or appear to be completed in a single step) without potential interruption.
** Wikipedia has a good basic overview of the need for atomicity in the article on [http://en.wikipedia.org/wiki/Linearizability Linerarizability]
** Atomics may be performed using special instructions or Kernel-compiler cooperation
==== Memory Barriers ====
'''Memory Barriers''' ensure that memory accesses are sequenced so that multiple threads, processes, cores, or IO devices see a predictable view of memory.
* Leif Lindholm provides an excellent explanation of memory barriers.
** Blog series - I recommend this series, especially the introduction, as a very clear explanation of memory barrier issues.
*** Part 1 - [http://community.arm.com/groups/processors/blog/2011/03/22/memory-access-ordering--an-introduction Memory Access Ordering - An Introduction]
*** Part 2 - [http://community.arm.com/groups/processors/blog/2011/04/11/memory-access-ordering-part-2--barriers-and-the-linux-kernel Memory Access Ordering Part 2 - Barriers and the Linux Kernel]
*** Part 3 - [http://community.arm.com/groups/processors/blog/2011/10/19/memory-access-ordering-part-3--memory-access-ordering-in-the-arm-architecture Memory Access Ordering Part 3 - Memory Access Ordering in the ARM Architecture]
** Presentation at Embedded Linux Conference 2010 (Note: Acquire/Release in C++11 and ARMv8 aarch64 appeared after this presentation):
*** [http://elinux.org/images/f/fa/Software_implications_memory_systems.pdf Slides]
*** [http://free-electrons.com/pub/video/2010/elce/elce2010-lindholm-memory-450p.webm Video]
* [http://www.rdrop.com/users/paulmck/scalability/paper/whymb.2010.07.23a.pdf Memory Barriers - A Hardware View for Software Hackers] - This is a highly-rated paper that explains memory barrier issues - as the title suggests, it is designed to describe the hardware origin of the problem to software developers. Despite the fact that it is an introduction to the topic, it is still very technical.
* [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka14041.html ARM Technical Support Knowlege Article - In what situations might I need to insert memory barrier instructions?] - Note that there are some additional mechanisms present in ARMv8 aarch64, including Acquire/Release.
* [https://www.kernel.org/doc/Documentation/memory-barriers.txt Kernel Documentation on Memory Barriers] - discusses the memory barrier issue generally, and the solutions used within the Linux kernel. This is part of the kernel documentation.
* Acquire-Release mechanisms
** [http://blogs.msdn.com/b/oldnewthing/archive/2008/10/03/8969397.aspx MSDN Blog Post] with a very clear explanation of Acquire-Release.
** [http://preshing.com/20130922/acquire-and-release-fences/ Preshing on Programming post] with a good explanation.
** [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.genc010197a/index.html ARMv8 Instruction Set Architecture Manual] (ARM InfoCentre registration required) - See the section on Acquire/Release and Load/Store, especially Load/Store Exclusive (e.g., LDREX)
==== The Future of Memory ====
* NUMA (on steroids!)
* Non-volatile, byte-addressed main memory
* Non-local memory / Memory-area networks
* Memory encryption
==== Building Software ====
* Configuration Systems
** make-based systems
*** [https://www.gnu.org/software/automake/manual/html_node/index.html#Top The GNU Build System: autotools, autoconf, automake]
*** Configuration name ("triplet") -- ''cpu-manufacturer-operatingSystem'' or ''cpu-manufacturer-kernel-operatingSystem''
**** config.guess and config.sub
*** CMake
*** qmake
*** Meson
*** iMake and Others
** Non-make-based systems
*** Apache Ant
*** Apache Maven
*** Qt Build System
* Building in the Source Tree vs. Building in a Parallel Tree
** Pros and Cons
** [https://www.gnu.org/software/automake/manual/html_node/VPATH-Builds.html#VPATH-Builds GNU automake ''vpath'' builds]
* Installing and Testing in non-system directories
** Configuring installation to a non-standard directory
*** Running <code>configure</code> with <code>--prefix</code>
*** Running <code>make install</code> as a non-root user
*** DESTDIR variable for <code>make install</code>
** Runtime environment variables:
*** PATH
*** LD_LIBRARY_PATH and LD_PRELOAD (see the [http://man7.org/linux/man-pages/man8/ld.so.8.html ld.so manpage])
** Security when running software
*** Device access
**** Opening a TCP/IP or UDP/IP port below 1024
**** Accessing a <code>/dev</code> device entry
***** Root permission
***** Group permission
*** SELinux Type Enforcement
**** Enforcement mode
***** View enforcement mode: <code>getenforce</code>
***** Set enforcement mode: <code>setenforce</code>
**** Changing policy
***** [https://fedoraproject.org/wiki/SELinux/audit2why audit2why]
***** [https://fedoraproject.org/wiki/SELinux/audit2why audit2allow]
=== Week 9: Class II ===
* Portability Issues
=== Week 9 Deliverables ===
* Blog about your project
== Week 10 ==
=== Week 10: Class I ===
* Project hacking and discussion
=== Week 10 Deliverables ===
* Blog about your project.
* Note: March blogs are due Monday, April 2. Remember that the target is 1-2 posts/week, which is 4-8 posts/month.
== Week 11 ==
=== Week 11 - Class I ===
* Project hacking and discussion
=== Week 11 - Class II ===
* [[Compiler Intrinsics]]
* Project discussion
== Week 12 ==
=== Week 12 - Class I ===
* Class cancelled
=== Week 12 - Class II ===
* Project hacking and discussion
-->
<!--
###################################################################################
###################################################################################
###################################################################################
###################################################################################
###################################################################################
== Week 6 ==
=== Week 6 - Class II ===
* [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab]] (Lab 6)
== Week 7 ==
=== Week 7 - Class I ===
Project discussion
=== Week 7 - Class II ===
Profiling
=== Week 7 Deliverables ===
Blog about your project.
=== Week 6 Deliverables ===
* Blog your results for the [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab]] (Lab 6) -- be sure to include links to your code, detailed results, and your reflection on the lab.
== Week x8 ==
=== Week x8 - Class I ===
* Review
* Plans for Remainder of Term
=== Week x8 - Class II ===
* [[Inline Assembly Language]]
* [[SPO600 Inline Assembler Lab|Inline Assembler Lab]] (Lab 7)
=== Week x8 Deliverables ===
* Blog about your Lab 7 results
== Week x9 ==
=== Week x9 - Class I ===
* Benchmarking and Profiling
** Notes to follow
=== Week x9 - Class II ===
* [[Fall 2017 SPO600 Project]]
=== Week x9 Deliverables ===
* Start blogging about your project!
###################################################################################
=== Week 2 - Class II ===
* [[SPO600 Assembler Lab|Assembly language lab]] (lab 3)
=== Week 2 Deliverables ===
* Blog your conclusion to the [[SPO600 Code Review Lab|Code Review Lab]] (Lab 1)
== Week 3 ==
=== Week 3 - Class I ===
* Continue group work on [[SPO600 Assembler Lab|Lab 3]].
=== Week 3 - Class II ===
* [[SPO600 Compiled C Lab]] (Lab 4)
=== Week 3 Deliverables ===
* Blog your conclusion to:
** [[SPO600 Assembler Lab|Lab 3]]
** [[SPO600 Compiled C Lab|Lab 4]]
== Week 4 ==
=== Week 4 - Class I ===
Software Optimization
* [[Compiler Optimizations]]
* [[Profile Guided Optimization]]
* Algorithm Selection
=== Week 4 - Class II ===
* [[SPO600 Algorithm Selection Lab]] (Lab 5)
=== Week 4 Deliverables ===
* Blog about your Lab 5 results.
== Week 5 ==
=== Week 5 - Class I ===
* Finish the [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab]]
=== Week 5 - Class II ===
* Introduction to Vector Processing/SIMD
* [[SPO600 Vectorization Lab|Vectorization Lab]] (Lab 6)
=== Week 5 Deliverables ===
* Blog your results for the [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab]] (Lab 5)
* Blog your results for the [[SPO600 Vectorization Lab|Vectorization Lab]] (Lab 6)
* For each of the above, be sure to include links to your code, detailed results, and your reflection on the lab.
== Week 6 ==
=== Week 6 - Class I ===
* [[Inline Assembly Language]] -- often used for:
*# Implementing a memory barrier
*# Performing an [[Atomic Operation]]
*#* '''Atomics''' are operations which must be completed in a single step (or appear to be completed in a single step) without potential interruption.
*#* Wikipedia has a good basic overview of the need for atomicity in the article on [http://en.wikipedia.org/wiki/Linearizability Linerarizability]
*# Gaining performance (by accessing processor features not exposed by the high-level language being used (C, C++, ...))
* [[SPO600 Inline Assembler Lab|Inline Assembler Lab]] (Lab 7)
=== Week 6 - Class II ===
* [[SPO600 Inline Assembler Lab|Inline Assembler Lab]] (Lab 7) continued...
=== Week 6 Deliverables ===
* Blog your Lab 7 results.
== Week 7 ==
=== Week 7 - Class I ===
==== Overview/Review of Processor Operation ====
* Fetch-decode-dispatch-execute cycle
* Pipelining
* Branch Prediction
* In-order vs. Out-of-order execution
** Micro-ops
==== Memory Basics ====
* Organization of Memory
** System organization
** Process organization
*** Text, data
*** Stack
*** Heap
* Memory Speeds
* Cache
** Cache lookup
** Cache synchronization and invalidation
** Cache line size
* Prefetch
** Prefetch hinting
==== Memory Architecture ====
* Virtual Memory and Memory Management Units (MMUs)
** General principles of VM and operation of MMUs
** Memory protection
*** Unmapped Regions
*** Write Protection
*** Execute Protection
*** Privilege Levels
** Swapping
** Text sharing
** Data sharing
** Shared memory for Inter-Process Communication
** Copy-on-Write (CoW)
** Demand Loading
** Memory mapped files
==== Memory Barriers ====
'''Memory Barriers''' ensure that memory accesses are sequenced so that multiple threads, processes, cores, or IO devices see a predictable view of memory.
* Leif Lindholm provides an excellent explanation of memory barriers.
** Blog series - I recommend this series, especially the introduction, as a very clear explanation of memory barrier issues.
*** Part 1 - [http://community.arm.com/groups/processors/blog/2011/03/22/memory-access-ordering--an-introduction Memory Access Ordering - An Introduction]
*** Part 2 - [http://community.arm.com/groups/processors/blog/2011/04/11/memory-access-ordering-part-2--barriers-and-the-linux-kernel Memory Access Ordering Part 2 - Barriers and the Linux Kernel]
*** Part 3 - [http://community.arm.com/groups/processors/blog/2011/10/19/memory-access-ordering-part-3--memory-access-ordering-in-the-arm-architecture Memory Access Ordering Part 3 - Memory Access Ordering in the ARM Architecture]
** Presentation at Embedded Linux Conference 2010 (Note: Acquire/Release in C++11 and ARMv8 aarch64 appeared after this presentation):
*** [http://elinux.org/images/f/fa/Software_implications_memory_systems.pdf Slides]
*** [http://free-electrons.com/pub/video/2010/elce/elce2010-lindholm-memory-450p.webm Video]
* [http://www.rdrop.com/users/paulmck/scalability/paper/whymb.2010.07.23a.pdf Memory Barriers - A Hardware View for Software Hackers] - This is a highly-rated paper that explains memory barrier issues - as the title suggests, it is designed to describe the hardware origin of the problem to software developers. Despite the fact that it is an introduction to the topic, it is still very technical.
* [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka14041.html ARM Technical Support Knowlege Article - In what situations might I need to insert memory barrier instructions?] - Note that there are some additional mechanisms present in ARMv8 aarch64, including Acquire/Release.
* [https://www.kernel.org/doc/Documentation/memory-barriers.txt Kernel Documentation on Memory Barriers] - discusses the memory barrier issue generally, and the solutions used within the Linux kernel. This is part of the kernel documentation.
* Acquire-Release mechanisms
** [http://blogs.msdn.com/b/oldnewthing/archive/2008/10/03/8969397.aspx MSDN Blog Post] with a very clear explanation of Acquire-Release.
** [http://preshing.com/20130922/acquire-and-release-fences/ Preshing on Programming post] with a good explanation.
** [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.genc010197a/index.html ARMv8 Instruction Set Architecture Manual] (ARM InfoCentre registration required) - See the section on Acquire/Release and Load/Store, especially Load/Store Exclusive (e.g., LDREX)
==== The Future of Memory ====
* NUMA (on steroids!)
* Non-volatile, byte-addressed main memory
* Non-local memory
* Memory encryption
=== Week 7 - Class II ===
* [[Winter 2017 SPO600 Project|Course Project]]
=== Week 7 Deliverables ===
* Blog your Lab 7 results, including the second part
* (To be announced: Project Deliverables)
== Week 8 ==
=== Week 8 - Class I ===
* Project Discussions
=== Week 8 - Class II ===
* Project Presentation #0
** Selected glibc function(s)
** Plan of Action
=== Week 8 Deliverables ===
* Blog about your selected function(s) and project plan
** Remember: You should be posting 1-2 times per week
#################################################################################
#################################################################################
#################################################################################
== Week 3 ==
=== Tuesday (Jan 26) ===
* Continue work on the [[SPO600 Assembler Lab|Assembly language lab]] (lab 3)
=== Friday (Jan 29) ===
* [[SPO600 Compiled C Lab|Compiled C lab]] (lab 4)
=== Week 3 Deliverables ===
* Blog about your [[SPO600 Assembler Lab|Assembly language lab]] (lab 3).
* Blog about your [[SPO600 Compiled C Lab|Compiled C lab]] (lab 4) experience and results. Consider the optimizations and transformations that the compiler performed.
* Remember that these posts (as all of your blog posts) will be marked both for communication (clarity, quality of writing (including grammar and spelling), formatting, use of links, completeness) and for content (lab completion and results). Your posts should contain both factual results as well as your reflections on the meaning of those results, the experience of performing the lab, and what you have learned.
'''Reminder:''' Blogs will be marked as they stand at the end of the month (Sunday).
== Week 4 ==
=== Tuesday (Feb 2) ===
Software Optimization
* [[Compiler Optimizations]]
* Algorithm Selection
=== Friday (Feb 5) ===
* [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab]] (Lab 6)
=== Week 4 Deliverables ===
* Blog about your Lab 5 results.
== Week 5 ==
=== Tuesday (Feb 9) ===
* Finish the [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab]]
* Discussion of Benchmarking Challenges
* Introduction to Vector Processing/SIMD
=== Friday (Feb 12) ===
* [[SPO600 Vectorization Lab|Vectorization Lab]] (Lab 6)
=== Week 5 Deliverables ===
* Blog your results for the [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab]] (Lab 5)
* Blog your results for the [[SPO600 Vectorization Lab|Vectorization Lab]] (Lab 6)
* For each of the above, be sure to include links to your code, detailed results, and your reflection on the lab.
== Week 6 ==
=== Tuesday (Feb 16) ===
* Discussion of Memory Architecture
=== Friday (Feb 19) ===
* [[Inline Assembly Language]] -- often used for:
*# Implementing a memory barrier
*# Performing an [[Atomic Operation]]
*# Gaining performance (by accessing processor features not exposed by the high-level language being used (C, C++, ...))
* [[SPO600 Inline Assembler Lab|Inline Assembler Lab]] (Lab 7)
=== Week 6 Deliverables ===
* Blog your Lab 7 results.
== Week 7 ==
=== Tuesday (Feb 23) ===
* Discussion of [[Winter 2016 SPO600 Compiler Options Presentation|Course Presentation]] assignment
=== Friday (Feb 26) ===
* Discussion of the [[Winter 2016 SPO600 Project|Course Project]]
=== Week 7 Deliverables ===
* Blog about your selected Presentation and Project topics.
== Week 8 ==
[http://connect.linaro.org/bkk16/|Linaro Connect] - No classes.
=== Week 8 Deliverables ===
* Prepare for your Presentation
* Work on your Project
* Blog about what you're doing!
== Week 9 ==
=== Tuesday (Mar 14) ===
* [[Winter 2016 SPO600 Compiler Options Presentation|Presentations]]
=== Friday (Mar 18) ===
* [[Winter 2016 SPO600 Compiler Options Presentation|Presentations]]
=== Week 9 Deliverables ===
* Blog about your Presentation, incorporating any discussion or feedback during the presentation.
== Week 10 ==
=== Tuesday (Mar 22) ===
* [[Winter 2016 SPO600 Project|Course Project]] - Stage I Updates
=== Week 10 Deliverables ===
* Blog your Stage I Updates. '''Important!''' - this will be used to assign your Stage I project mark! Include:
** Which software package you are working on
** Your experience building the software "out of the box" on x86_64 and AArch64 platforms
** Baseline results (performance)
** Which area of the software you will be working on and which approach you are going to take to optimizing the software...
**# Improving the Build Instructions (e.g., compiler options), OR
**# Changing the Software (substituting a different algorithm, or refactoring for better compiler optimization e.g., auto-vectorization), OR
**# Adding Platform-Specific code for AArch64
== Week 11 ==
=== Tuesday (Mar 29) ===
* Discussion & Hack Session
=== Thursday (Mar 31) ===
Reminder: '''Special Event:''' [https://www.eventbrite.ca/e/leadership-lunch-with-mike-shaver-engineer-director-for-facebook-tickets-23046621064 Leadership Lunch with Mike Shaver]
=== Friday (Apr 1) ===
* Discussion & Hack Session
=== Week 11 Deliverables ===
* Blog about your project work.
== Week 12 ==
=== Tuesday (Apr 5) ===
* Discussion & Hack Session
=== Friday (Apr 8) ===
* Project Stage II Updates
=== Week 12 Deliverables ===
* Blog your Stage II Project Updates by '''Midnight, Sunday, Apr 10.''' Note that this will be used for your Stage II project mark (20%).
== Week 13 ==
=== Tuesday (Apr 12) ===
* Wrap-Up Discussion
=== Friday (Apr 15) ===
* Stage III Project Updates
=== Week 13 Deliverables ===
* Blog your Stage III Project Updates by Midnight on Thursday, April 21.
* Complete ALL your blogging for this course by Midnight on Thursday, April 21. Make sure that you have included all of the labs, your presentation, and your project work. Remember that there should be at least 1-2 posts per week. Your blogging from April 1-April 21 will be used for your April communication mark.
== Week 2 ==
=== Tuesday (Sep 15) ===
{{Admon/tip|Bring Your Laptop|Classes are held in a [[Active Learning Classroom]]. If you have a laptop or other device with a VGA or HDMI output (such as a smartphone!) please bring it. You'll need either a local linux environment or an [[SSH]] client -- which is built-in to Linux, Mac, and Chromebook systems, and readily available for Windows, Android, and iOS devices.}}
* [[SPO600 Compiled C Lab|Compiled C Lab (Lab 2)]]
* Sheets from Last Week
** Open Source Student Agreement
=== Friday (Sep 18) ===
* Introductions
* [[Compiler Optimizations]]
* Introduction to the [[Fall 2015 SPO600 Compiler Options Presentation|Compiler Options Presentation]]
=== Week 2 Deliverables ===
* Blog about your [[SPO600 Code Review Lab|Code Review Lab (Lab 1)]] and [[SPO600 Compiled C Lab|Lab 2]] experience and results. For lab 2, consider the optimizations and transformations that the compiler performed. Remember that these posts (as all of your blog posts) will be marked both for communication (clarity, quality of writing (including grammar and spelling), formatting, use of links, completeness) and for content (lab completion and results). Your posts should contain both factual results as well as your reflections on the meaning of those results, the experience of performing the lab, and what you have learned.
== Week 3 ==
This week [[User:Chris Tyler|your professor]] is at [http://connect.linaro.org/sfo15/ Linaro Connect], an engineering conference run by [http://www.linaro.org Linaro] - a distributed not-for-profit collaborative technology company focused on Linux on ARM.
* [[Fall 2015 SPO600 Compiler Options Presentation|Select and prepare to teach the class about two compiler options]].
=== Week 3 Deliverables ===
* Be prepared to give your [[Fall 2015 SPO600 Compiler Options Presentation|presentation]] on Tuesday of next week (September 29).
== Week 4 ==
=== Tuesday (Sep 29) ===
* Presentations
=== Friday (Oct 2) ===
* Presentations
* Introduction to ARM64 hardware
* [[SPO600 Algorithm Selection Lab|Algorithm Selection Lab (Lab 3)]]
=== Week 4 Deliverables ===
* Blog your [[Fall 2015 SPO600 Compiler Options Presentation|presentation]], incorporating any feedback and Q&A input that was given during/after the presentation in class.
== Week 5 ==
=== Tuesday (Oct 6) ===
* Class discussion/hacking on [[SPO600 Algorithm Selection Lab|Lab 3]].
=== Friday (Oct 9) ===
* More on Lab 3
* Discussion of Benchmarking
=== Week 5 Deliverables ===
* Blog your [[SPO600 Algorithm Selection Lab|Lab 3]] results.
== Week 6 ==
=== Tuesday (Oct 13) ===
* Discussion of benchmarking
** Control of variables
*** Competition for system resources
*** Repeatability
* Planning for a Compiler Options Test Framework
=== Friday (Oct 16) ===
* Compiler Options Framework
** Divide up tasks
** Start development
=== Week 6 Deliverables ===
* Blog your recommendations for the test framework design.
== Week 7 ==
=== Tuesday (Oct 20) ===
* Build the [[SPO600 Framework Project|Compiler Options Test Framework]]
=== Friday (Oct 23) ===
* Project selection
** Your task over reading week: Become an expert in building your selected software, and then make it work with the [[SPO600 Framework Project|Compiler Options Test Framework]]
=== Week 7 Deliverables ===
* Blog about the compiler options framework, and your work on that project.
* Blog about your selected project.
== Week 8 ==
=== Tuesday (Nov 3) ===
* No class scheduled - your [[User:Chris Tyler|prof]] is in Whitehorse, YK at an NSERC workshop.
* Please work on your [[Fall 2015 SPO600 Course Project|project]], and be ready to present on Friday.
=== Friday (Nov 6) ===
* Present your Stage I results for your [[Fall 2015 SPO600 Course Project|project]].
=== Week 8 Deliverables ===
* Blog about your [[Fall 2015 SPO600 Course Project|stage I project results]]. This will be used to assign the first marks for your project.
== Week 9 ==
=== Tuesday (Nov 10) ===
* [[Computer Architecture]] overview (see also the [[:Category:Computer Architecture|Computer Architecture Category]])
=== Friday (Nov 13) ===
* [[SPO600 Assembler Lab|Assembly language lab]] (lab 4)
=== Week 9 Deliverables ===
* Blog about your project progress (2+ posts per week).
* Blog the [[SPO600 Assembler Lab|Assembly language lab]] -- include your results, a link to your source code, and your reflections on the experience.
== Week 10 ==
=== Tuesday (Nov 17) ===
* Discussion & Hack Session
** [[SPO600 Assembler Lab|Assembly language lab (Lab 4) results]]
** Testing Framework
=== Friday (Nov 20) ===
* Hack session on the Testing Framework
=== Week 10 Deliverables ===
* Blog about your project work
* Blog about your Lab 5 results
== Week 11 ==
=== Tuesday (Nov 22) ===
* SIMD and Vectorization
* [[SPO600 Vectorization Lab|Vectorization Lab (Lab 6)]]
=== Friday (Nov 25) ===
* Discussion of the State of the Framework
* Hack Session
=== Week 11 Deliverables ===
* Blog your [[SPO600 Vectorization Lab|Lab 6]] results.
== Week 12 ==
=== Tuesday (Dec 1) ===
* Stage II Results - Brief Presentations
=== Friday (Dec 4) ===
* '''No Class''' - Early start to Exam Week
=== Week 12 Deliverables ===
* Blog about your Project Status - Stage II Results
** Provide results for the various flag combinations you tested
** Discuss the results, highlighting any anomalies
== Final Deliverables ==
* Blog about your Project Status - Stage III Results
** Important: Incorporate any feedback on your Stage II results
** Outline what you learned from your investigation into various combination of GCC flags
** Discuss what the upstream projects should do based on these results
** Communicate the results to the upstream project, if appropriate
** Outline further investigation that should be undertaken
* Blog a reflective blog post on the course
** What you have learned
** What you already knew
** What was good or bad about the way the course proceeded]
** How you might use this knowledge in the future
* This is the last chance to submit any lab postings, etc.
'''All blog postings must be in by Friday, December 18, at 11:59 pm to be included in the final grade.'''
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