Changes

As you may have seen from the workshop "False Sharing" a major performance hit can occur in parallel when data that sits on the same cache line in memory is used by two threads. When threads are attempting operations on the same cache line the threads will compete for access and will move the cache line around. The time taken to move the line is a significant amount of clock cycles which causes the performance problem. Through TBB, Intel created an allocated known as '''cache_aligned_allocater<type>'''. When used, any objects with memory allocation from it will never encounter false sharing. Note that if only 1 object is allocated by this allocater, false sharing may still occur. For compatability's sake(so that programmers can simply use "find and replace"), the cache_aligned_allocater takes the same arguments as the STL allocater. If you wish to use the allocater with STL containers, you only need to set the 2nd argument as the cache_allocater object.  The following is an example provided by Intel to demonstrate this: