You can find a sample project page template [[GPU621/DPS921_Sample_Project_Page | here]]
== [[GPU621/Sample_Project | Sample Project]] ==
'''Project Title here'''
# [mailto:chris.szalwinski@myseneca.ca?subject=GPU621 Chris Szalwinski]
# [mailto:fardad.soleimanloo@myseneca.ca?subject=GPU621 Fardad Soleimanloo]
# [mailto:chris.szalwinski@myseneca.ca;fardad.soleimanloo@myseneca.ca?subject=GPU621 eMail All]
== [[Team_Hortons | Team Hortons]] ==
'''Intel® Data Analytics Acceleration Library'''
# [mailto:racali@myseneca.ca?subject== Group Members == DPS921 Rosario A. Cali]
# [mailto:jpildush@myseneca.ca?subject=DPS921 Joseph Pildush]
# [mailto:racali@myseneca.ca?subject=DPS921 Rosario Cali]
# [mailto:jpildush@myseneca.ca;racali@myseneca.ca?subject=DPS921 eMail All]
== Progress ==
0%
== [[OpenMP Debugging Parallel Programs in Visual Studio / Team Debug|Team Debug]] =='''OpenMP Debugging Parallel Programs in Visual Studio'''
# [mailto:xngo-trong@myseneca.ca?subject=GPU621 Sofia Ngo-Trong]
# [mailto:ashimazaki@myseneca.ca?subject=GPU621 Azusa Shimazaki]
'''Go Programming Language'''
# [mailto:ssaqib1@myseneca.ca?subject=DPS921 Suhaib Saqib]
# [mailto:ralmira@myseneca.ca?subject=DPS921 Roana Almira]
# [mailto:lpnewell@myseneca.ca?subject=DPS921 Liam Newell]
# [mailto:ssaqib1@myseneca.ca;ralmira@myseneca.ca;lpnewell@myseneca.ca?subject=DPS921 eMail All]
== [[Team NP Complete]] ==
== [[Team False Sharing]] ==
In symmetric multiprocessor systems (SMP), each processor has a local cahce. The memory system must guarantee cache coherence. False sharing occurs when threads on different processors modify variables that reside on the same cache line. This invalidates the cache line and forces an update, which hurts performance.
False sharing is a well-know performance issue on SMP systems, where each processor has a local cache. it occurs when treads on different processors modify varibles that reside on th the same cache line like so.
In Figure, threads 0 and 1 require variables that are adjacent in memory and reside on the same cache line. The cache line is loaded into the caches of CPU 0 and CPU 1. Even though the threads modify different variables, the cahche line is invalidatedm forcing a memory update to maintain cache coherency.
To ensure data consistency across multiple caches, multiprocessor-capable Intel® processors follow the MESI (Modified/Exclusive/Shared/Invalid) protocol. On first load of a cache line, the processor will mark the cache line as ‘Exclusive’ access. As long as the cache line is marked exclusive, subsequent loads are free to use the existing data in cache. If the processor sees the same cache line loaded by another processor on the bus, it marks the cache line with ‘Shared’ access. If the processor stores a cache line marked as ‘S’, the cache line is marked as ‘Modified’ and all other processors are sent an ‘Invalid’ cache line message. If the processor sees the same cache line which is now marked ‘M’ being accessed by another processor, the processor stores the cache line back to memory and marks its cache line as ‘Shared’. The other processor that is accessing the same cache line incurs a cache miss.
The frequent coordination required between processors when cache lines are marked ‘Invalid’ requires cache lines to be written to memory and subsequently loaded. False sharing increases this coordination and can significantly degrade application performance.
'''Analyzing False Sharing '''
# [mailto:hnaidu@myseneca.ca?subject=DPS921 Harika Naidu]
# [mailto:sgupta44@senecacollege.ca?subject=DPS921 Shivam Gupta]
# [mailto:ykim6@myseneca.ca?subject=DPS921 Yong Kuk Kim]
= Presentation Schedule =
{| border="1"
|-
|Team Name
|Date and Time
|-
|[https://wiki.cdot.senecacollege.ca/wiki/Team_Hortons Team Hortons]
|December 15 11:40
|-
|[https://wiki.cdot.senecacollege.ca/wiki/DPS921/Game_of_Threads Game of Threads]
|December 15 12:00
|-
|[https://wiki.cdot.senecacollege.ca/wiki/Team_MMD Team MMD]
|December 15 12:20
|-
|
|December 15 12:40
|-
|
|December 15 13:00
|-
|[https://wiki.cdot.senecacollege.ca/wiki/Team_Go Team Go]
|December 18 13:30
|-
|
|December 18 13:50
|-
|[https://wiki.cdot.senecacollege.ca/wiki/Alpha_Centauri Alpha Centauri]
|December 18 14:10
|-
|[https://wiki.cdot.senecacollege.ca/wiki/Team_Darth_Vector Darth Vector]
|December 18 14:30
|-
|[https://wiki.cdot.senecacollege.ca/wiki/DPS921/team_false_sharing Team False Sharing]
|December 18 14:50
|-
|[https://wiki.cdot.senecacollege.ca/wiki/GPU621/Team_Debug Team Debug]
|December 22 11:40
|-
|[https://wiki.cdot.senecacollege.ca/wiki/Team_Lion_F2017 Team Lion]
|December 22 12:00
|-
|[https://wiki.cdot.senecacollege.ca/wiki/Team_NP_Complete Team NP Complete]
|December 22 12:20
|-
|}
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