Changes

When the CPU accesses the data at that time data goes into the cache and this memory block is known as the cache line. But it is not possible that modify the original data when changes in the cache line. Here cache coherence helps that stored in multiple local caches. Cache coherence connects all cache. == MESI ==First, we know that the cache line has four different states. Like, exclusive, shared, modified, and invalid. So MESI is an acronym for all four states. To understand it well we throw light on this example.  [[File:MESI1.jpg|center|400px]]<br /> This picture shows that the core A read value a from the main memory. So this core also fetches some nearby values from the main memory and stores these values in the cache line and makes it exclusive because only core A operates this cache line.  [[File:MESI2.jpg|center|400px]]<br /> Later, core B also reads the value of b from memory. Now, a and b both read the same cache line and close so, both cores are shared.  [[File:MESI3.jpg|center|400px]]<br /> Moreover, core A change the value of a so, this change is stored in the buffer and cache line tagged as modified. In the end, it communicates with core B and is known as an invalid cache line.