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→Evaluation
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|5||Sep 30||[[#Week 5 - Class I|SIMD and Vectorization / Inline Assembler]]||[[#Week 5 - Class II|Investigation: Inline AssemblerSIMD Lab]] (Lab 5)||[[#Week 5 Deliverables|Blog your lab 5 results.]]
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|6||Oct 7||[[#Week 6 - Class I|Compiler Optimizations / Computer Resources and Performance / Baseline Builds / Benchmarking and Profiling]]||[[#Week 6 - Class II|Software Build SIMD Lab (Continued) (Lab 65)]]||[[#Week 6 Deliverables|Blog your Lab 6 5 results.]]
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|7||Oct 14||[[#Week 7 - Class I|Building Software / Projects!]]||[[#Week 7 - Class II|Project selection]]||[[#Week 7 Deliverables|Catch up on any missed labs, blog about your project selection progress.]]
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|8||Oct 28||[[#Week 8 - Class I|Intrinsics and SIMDMemory Ordering / Barriers / Acquire-Release Semantics]]||[[#Week 8 - Class II|Project Hacking]]||[[#Week 8 Deliverables|Blog blog about your project.]]
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|10||Nov 11||[[#Week 10 - Class I|Memory Ordering / Barriers / Acquire-Release SemanticsIntrinsics]]||[[#Week 10 - Class II|Project Hacking]]||[[#Week 10 Deliverables|Blog about your project.]]
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!Category!!Percentage!!Evaluation Dates
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|Communication||align="right"|20%||September (Oct 2 - 5%), October (November 10 - 5%), November (5%), end of course (5%).
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|Quizzes||align="right"|10%||May be held during any class, usually at the start of class. A minimum of 5 one-page quizzes will be given. No make-up/retake option is offered if you miss a quiz. Lowest 3 scores will not be counted. Students with Test Centre accommodations may choose to write the quizzes in the class, or alternately write a monthly quiz in the Test Center.
|Labs||align="right"|10%||See deliverables column above. All labs must be submitted by the end of the course, but it is best if you stay on top of the labs and submit according to the table above.
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|Project work||align="right"|60%||3 stages: 15% (Nov 18), 20% (Nov 2229), 25% (Dec 11).
|}
* [[Make and Makefiles]]
* [[Assembly Language]]
* [[SPO600 Assembler Lab|Assembler Lab]] (Lab 43)
=== Week 2 - Class II ===
** Each architecture has a different notation for SIMD registers. In AArch64 (which will be our focus):
*** Vector usage uses the notation v''n''.''s'' where ''n'' is the register number and ''s'' is the shape of the lanes, expressed as the number of lanes and a letter indicating the width of the lanes: q for quad-word (128 bits), d for double-word (64 bits), s for single-word (32 bits), h for half-word (16 bits), and b for byte (8 bits). Therefore, <code>v0.16b</code> is vector register 0 used as 16 lanes of 8 bits (1 byte) each, while <code>v8.4s</code> is vector register 8 used as 4 lanes of 32 bits each. Most instructions permit either 64 or 128 bits of the register to be used.
*** Scalar usage uses the lane width letter followed by the vector register number. Therefore, <code>q3</code> refers to vector register 3 used as a single 128-bit value, and <code>s3</code> refers to the same register used as a single 32-bit register. Note that these are the same register referred to as v3 for vector usage. When using less than 128 bits, the remaining bits are either zero-filled (unsigned usage) or sign-extended (signed usage: the upper bits are filled with the sign bit, i.e., the same value as the high bit of the active part of the register).** Most SIMD operations work on corresponding lanes of the operand registers. For example, the AArch64 instruction <code>add v0.8h, v1.8h, v2.8h</code> will take the value in the first lane of register 1, add the value in the first lane of register 2, and place the result in the first lane of register 0. At the same time, the other lanes are processed in the same way, resulting in 8 simultaneous addition operations being performed.
** A small number of SIMD operations work across lanes, e.g., to find the lowest or highest value in all of the lanes, to add the lanes together, or to duplicate a single value into all of the lanes of a register. These are usually used to set up or summarize the results of SIMD operations -- for example, a value of 0 might be duplicated into all of the lanes of a result register, then a loop applied to sum array data into the results register, and then a lane-summing operation performed to merge the results from all of the lanes.
* SIMD capabilities can be used in a program in one of three different ways:
*#* The compiler will be very cautious about vectorizing code. See the Resources section below for insight into these challenges.
*#** In order to vectorize a loop, among other things, the number of loop iterations needs to be known before the loop starts, memory layout must meet SIMD alignment requirements, loops must not overlap in a way that is affected by vectorization.
*#** The compiler will also calculate a cost for the vectorization: in the case of a small loop, because the extra setup before the loop and processing after the loop may negate the benefits of vectorization.
*#* Vectorization in applied by default only at the -O3 level in most compilers. In GCC:
*#** The main individual feature flag to turn on vectorization is <code>-ftree-vectorize</code> (enabled by default at -O3, disabled at other levels).
*#** You can see all of the vectorization decisions using <code>-fopt-info-vec-all</code> or you can see just the missed vectorizations using <code>-fopt-info-vec-missed</code> (which is usually what you want to focus on, because it show only the loops where vectorization was ''not'' enabled, and the reason that it was not). This approach is generally very portable.
*# We can explicitly include SIMD instructions in a C program by using [[Inline Assembly Language|Inline Assembler]]. This is obviously architecture-specific, so it is important to use C preprocessor directives to include/exclude this codedepending on the platform for which it is compiled, and to use a generic C implementation on any platform for which you are not providing an inline assembler version.*# ''C Intrinsics'' are function-like capabilities built into extensions to the C language. Although they look like functions, they are compiled inline, and they are used to provide access to features which are not provided by the C compilerlanguage itself. There is a group of intrinsics which provide access to SIMD instructions. However, the benefit of using these over inline assembler is debatable. SIMD intrinsics are not portable, and should be included with C preprocessor directives like inline assembler. * [[Inline Assembly Language]] * C Intrinsics** C Intrinsics are function-like extensions to the C language. Although they look like functions, they are compiled inline, and they are used to provide access to features which are not provided by the C language itself. See the Resources section below for additional detail.
=== Week 5 - Class II ===
== Week 6 ==
=== Week 6 - Class I ===
* [[Compiler Optimizations]]
* Advanced Compiler Optimizations
** [[Profile Guided Optimization]]
** [[Link Time Optimization]]
* [[Profiling]]
=== Week 6 - Class II ===
* Continue work on the [[SPO600 SIMD Lab|SIMD Lab]] (Lab 5)
=== Week 6 Deliverables ===
* Blog about your results to Lab 5
== Week 7 ==
=== Week 7 - Class I ===
Building software...
* Configuration Systems
** make-based systems
*** [https://www.gnu.org/software/automake/manual/html_node/index.html The GNU Build System: autotools, autoconf, automake]
**** GNU autotools makes extensive use of the ''configuration name'' ("triplet") -- ''cpu-manufacturer-operatingSystem'' or ''cpu-manufacturer-kernel-operatingSystem'' (e.g.,
**** config.guess and config.sub
*** CMake
*** qmake
*** Meson
*** iMake and Others
** Non-make-based systems
*** Apache Ant
*** Apache Maven
*** Qt Build System
* Building in the Source Tree vs. Building in a Parallel Tree
** Pros and Cons
** [https://www.gnu.org/software/automake/manual/html_node/VPATH-Builds.html#VPATH-Builds GNU automake ''vpath'' builds]
* Installing and Testing in non-system directories
** Configuring installation to a non-standard directory
*** Running <code>configure</code> with <code>--prefix</code>
*** Running <code>make install</code> as a non-root user
*** DESTDIR variable for <code>make install</code>
** Runtime environment variables:
*** PATH
*** LD_LIBRARY_PATH and LD_PRELOAD (see the [http://man7.org/linux/man-pages/man8/ld.so.8.html ld.so manpage])
** Security when running software
*** Device access
**** Opening a TCP/IP or UDP/IP port below 1024
**** Accessing a <code>/dev</code> device entry
***** Root permission
***** Group permission
*** SELinux Type Enforcement
**** Enforcement mode
***** View enforcement mode: <code>getenforce</code>
***** Set enforcement mode: <code>setenforce</code>
**** Changing policy
***** [https://fedoraproject.org/wiki/SELinux/audit2why audit2why]
***** [https://fedoraproject.org/wiki/SELinux/audit2why audit2allow]
* Build Dependencies
* Packaging
* General information about the SPO600 projects
** Goal
** Stages
** Approaching the Project
=== Week 7 - Class II ===
* [[Fall 2019 SPO600 Project|Project Selection]]
=== Week 7 Deliverables ===
* Catch up on any incomplete labs (and blog about them)
* Blog about your project selection progress
== Week 8 ==
=== Week 8 - Class I ===
==== Overview/Review of Processor Operation ====
* Fetch-decode-dispatch-execute cycle
* Pipelining
* Branch Prediction
* In-order vs. Out-of-order execution
** Micro-ops
==== Memory Basics ====
* Organization of Memory
** Process organization
*** Text, data
*** Stack
*** Heap
** System organization
*** Kernel memory in process maps
*** Use of unallocated memory for buffers and cache
* Memory Speeds
* Cache
** Cache lookup
** Cache synchronization and invalidation
** Cache line size
* Prefetch
** Prefetch hinting
==== Memory Architecture ====
* Virtual Memory and Memory Management Units (MMUs)
** General principles of Virtual Memory and operation of MMUs
** Memory protection
*** Unmapped Regions
*** Write Protection
*** Execute Protection
*** Privilege Levels
** Swapping
** Text sharing
** Demand Loading
** Data sharing
*** Shared memory for Inter-Process Communication
*** Copy-on-Write (CoW)
** Memory mapped files
==== Memory Statistics ====
* Resident Set Size (RSS) and Virtual Set Size (VSS)
* Total memory consumption per process
* Total system memory consumption
==== Software Impact ====
* Alignment checks
* Page boundary crossing
=== Week 8 - Class II ===
* Project Discussion
=== Week 8 Deliverables ===
* Blog about your project work
<!--
* Organization of Memory
** Process organization
*** Text, data
*** Stack
*** Heap
** System organization
* Memory Speeds
* Cache
* Virtual Memory and Memory Management Units (MMUs)
** General principles of VM Virtual Memory and operation of MMUs
** Memory protection
*** Unmapped Regions
** Swapping
** Text sharing
** Demand Loading
** Data sharing
*** Shared memory for Inter-Process Communication*** Copy-on-Write (CoW)** Demand Loading
** Memory mapped files
