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|5||Oct 2|||[[#Week 5 - Class I|Algorithm Selection Lab (Lab 5)Compiler Optimizations]]||[[#Week 5 - Class II|SIMD and Auto-Vectorization (Lab 6)]]||[[#Week 5 Deliverables|Blog your the Algorithm Selection Lab (Lab 5) and the Auto-Vectorization Lab (Lab 6).]]
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* Complete and blog your results, conclusions, and reflections on the [[SPO600 Code Building Lab|Code Building Lab (Lab 4)]].
== Week 5 ==
=== Week 5 - Class I ===
* [[Compiler Optimizations]]
* [[Profile Guided Optimization]]
* [[Link Time Optimization]]
=== Week 5 - Class II ===
* Introduction to Vector Processing/SIMD
* [[SPO600 Vectorization Lab|Vectorization Lab]] (Lab 5)
=== Week 5 Deliverables ===
* Blog your results for the [[SPO600 Vectorization Lab|Vectorization Lab]] (Lab 5) -- be sure to include links to your code, detailed results, and your reflection on the lab.
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=== Week 4 Deliverables ===
, processor internals,, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II| instruction set architecture]]||[[#Week 2 - Class II|
* Blog about your Lab 5 results.
