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{|cellspacing="0" width="100%" cellpadding="5" border="1" style="background: #e0e0ff"
|-Code Building LabCode Building LabCode Building Lab
!Week!!Week of...!!width="28%"|Class I<br/>Monday 9:50-11:35!!width="28%"|Class II<br/>Wednesday 11:40-1:25!!width="28%"|Deliverables<br/>(Summary - click for details)
|-
|-
|2||Sep 11||[[#Week 2 - Class I|Computer Architecture Overview - Binary representation, processor internals, instruction set architecture]]||[[#Week 2 - Class II|Compiled C Lab (Lab 2)]]<!-- Overview of Working with Code and Building Software - Toolchains, compiler stages, switches and flags, binary file contents (Lab 2)]]-->||[[#Week 2 Deliverables|Blog your conclusion to Labs 1 and 2.]]
|-
|3||Sep 18||[[#Week 3 - Class I|Assembly Lab (Lab 3)]]||[[#Week 3 - Class II|Compiled C Lab Working with Code (Lab 4)]]||[[#Week 3 Deliverables|Blog about the Assembly Lab (Lab your results and conclusions for Labs 3) and Compiled C Lab (Lab 4)]]
|-
== Week 2 ==
, processor intern, processor internals, instruction set architecture]]||[[#Week 2 - Class II|als, instruction set architecture]]||[[#Week 2 - Class II|
=== Week 2 - Class I ===
=== Week 2 - Class II ===
<!--
* Working with Code
*# Getting Code
*#* Installation Scripts
* [[Overview of the Build and Release Process]]
* Looking at How Distributions Package the Code
** Using fedpkg
* How do you Test without Compromising the Running System?
** Paths
* [[SPO600 Code Building Lab|Code Building Lab (Lab 2)]] as homework
-->* [[SPO600 Compiled C Lab|Compiled C Lab (Lab 2)]]
=== Week 2 Deliverables ===
* Blog your conclusion to the [[SPO600 Code Review Lab|Code Review Lab (Lab 1)]]
* Blog the results and conclusion from the [[SPO600 Code Building Compiled C Lab|Code Building Compiled C Lab (Lab 2)]]
<!--
=== Week 4 Deliverables ===
, processor internals,, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II|, processor internals, instruction set architecture]]||[[#Week 2 - Class II| instruction set architecture]]||[[#Week 2 - Class II|
* Blog about your Lab 5 results.
