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→Common Elements in Modern Computer Design
* A central processing unit (CPU) which reads binary [[Machine Language|machine language]] instructions from memory and executes them. The CPU contains multiple [[Register|registers]]. Instructions are executed according to a [[Clock|clock]] pulse, which synchronizes activity across the system.
* RandomMemory, including random-access memory (RAM), which consists of multiple [[Word|words]] of memory which are individually [[Address|addressable]] -- words can be individually written to or read from each address. Memory is used to store both instructions and data. Memory is generally [[Volatile|volatile]], but some non-volatile memory is usually provided for system startup. * Some memory may be is connected to two the CPU as well as one or more devices for "memory mapped" input/output -- the CPU as one device, and a peripheral such as a video system or disk controller as the second device. Most modern computers use a [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka11516.html Von Neuman] architecture, with one memory space for both instructions (software) and data.In some systems, devices may be accessed through a separate address range (designated for I/O ports), which acts like memory-mapped I/O but has a distinct addressing scheme. Devices can get the CPU's attention using an [[Computer_Architecture#Interrupts_and_Exceptions|Interrupt]] scheme. Devices include:** Storage, which is addressable in sectors or blocks, and is used for [[Volatile|non-volatile]], long-term storage of instructions and data.* I/O ports * Human interface devices (HID), such as keyboards, pointing devices (mice, touchscreens, trackpads, and so forth), and busesfingerprint readers. These are typically low-speed devices (e.g., people type at 6 characters per second or less).** Video, used which typically uses a region of memory as a framebuffer to connect store the image being displayed. The video system may also be able to peripheralsperform hardware-accelerated operations such as bit-blitting, fills, video overlays, and 3D operations.** Audio, which typically uses a region of memory as an audio sample buffer.** Connectivity, including network, serial, and radio (including WiFi and Cellular) connections.
However, there is an enormous amount of variation even within this general design.
== Popular Architecture Families ==
Throughout this page and the [[:Category:Computer Architecture|Computer Architecture Category]] on this wiki, several architecture families are mentioned, including:
* x86 - The Intel/AMD architecture which debuted with the Intel 8086 processor (16-bit), gained desktop and server dominance as the 386/486/x86 32-bit architecture, and was extended by AMD to the 64-bit x86_64 architecture. Intel and AMD vigorously compete with x86_64 CPUs, which continue as the preeminent server architecture and most popular desktop architecture.
* ARM - An architecture which started with the Acorn computer company, became the dominant mobile and embedded architecture in its 32-bit incarnations, and was extended to 64-bit in version 8 ([[ARMv8]]) with the [[AArch64]] mode. 64-bit ARM processors are dominant in smartphone applications and starting to be compete in server and high-performance computing systems.
* PowerPC - An architecture which has been used in a wide range of applications, from Apple desktop systems to Sony PlayStation CELL processors, and which is now used primarily in IBM midrange and mainframe systems.
* MIPS - An architecture which was used in Sillicon Graphics workstations but has found its primary audience in network infrastructure such as backbone routers and firewall systems.
As well as some architectures which are no longer current:
* 6502 - An 8-bit architecture which helped spawned the home computing/personal computing era.
* Sparc - A RISC architecture developed by Sun Microsystems which powered the high-end workstation and server market for many years.
== Basic CPU Features ==
== Interrupts and Exceptions ==
Hardware interrupt requests (IRQs) are external signals which cause the CPU to stop executing the current program (generally between instructions) and jump to a pre-defined block of code. These signals were originally dedicated electrical signals but in newer systems may take the form of serially-signalled data (for example, on a PCIe bus). An interrupt is typically used to make the operating system service I/O requests when they occur. For example, when a sector of data is available from a disk drive, the disk controller will trigger an interrupt on the CPU, which will cause the operating system to load the received data. This may then cause the operating system to change the status of a process from blocked (waiting for data) to eligible for execution, so that it will be considered along with all other eligible processes when the next process switch is performed.
Most architectures support multiple levels of interrupts, usually numbered (e.g., "IRQ0", "IRQ8", and so forth). These may be handled by the CPU itself, or a (programmable) interrupt controller (''PIC'' , ''APIC'', or ''APICGIC'') may latch the IRQ event and signal the processor, which then queries the interrupt controller to determine which interrupt occurred. Some architectures support multiple types or levels priorities of interrupts -- for example, the 6502 supports regular (IRQ) and higher-priority non-maskable interrupts (NMI), while ARM processors offer both regular (IRQ) and "fast" interrupts (FIQ).
Software interrupts are similar to hardware interrupts, but are triggered by a specific instruction. x86, ARM, and PPC processors use software interrupts to invoke system calls.
An interrupt handler is part of the operating system typically runs at a higher privilege level than a regular application.
Exceptions (or ''traps'') are similar to interrupts, but are triggered by event occurrences within the processor. These exceptions cause code within the operating system to be executed to handle the event. Events which will trigger an exception include:
* Attempted execution of an undefined or invalid instruction.
When any type of interrupt is received, the [[Register#Program Counter|program counter]] is saved (typically by pushing it on the [[Stack|stack]] or storing it in a dedicated register), and then a new value for the program counter is loaded from an ''interrupt vector'' stored in a register or a pre-defined memory location, usually at the top or bottom of physical [[Address|address space]]. Effectively, this means that a subroutine jump is performed to the interrupt-handling routine. In systems where multiple devices are connected to one hardware interrupt line, it is necessary to poll the PIC/APIC or the attached devices to determine which one(s) triggered the interrupt before servicing the request(s). When the interrupt routine exits, the original program counter location is restored, and execution of the interrupted program continues.
Most but not all interrupts can be masked -- temporarily turned off -- either in the CPU or in the PIC/APIC/GIC.
Many debugging tools use a software interrupt for single-stepping through a program - for example, on a 6502, the instruction after the one to be executed by single-stepping is replaced with a BRK instruction (opcode 00), so that control will immediately return to the debugger after one instruction is executed. In other cases, the debugger regains control by scheduling a timer-based hardware non-maskable interrupt (NMI) to occur during the execution of the next instruction, using a peripheral timer chip.
