1,885
edits
Changes
→Interrupts and Exceptions
Most architectures support multiple levels of interrupts, usually numbered (e.g., "IRQ0", "IRQ8", and so forth). These may be handled by the CPU itself, or a (programmable) interrupt controller (''PIC'' or ''APIC'') may latch the IRQ event and signal the processor, which then queries the interrupt controller to determine which interrupt occurred. Some architectures support multiple types of levels of interrupts -- the 6502 supports regular (IRQ) and higher-priority non-maskable (NMI) interrupts, while ARM processors offer both regular (IRQ) and "fast" interrupts (FIQ).
Software interrupts are similar to hardware interrupts, but are triggered by a specific instruction on certain architectures. x86 , ARM, and PPC processors use software interrupts to invoke system calls.
Exceptions (or ''traps'') are similar to interrupts, but are triggered by event occurrences within the processor. These exceptions cause code within the operating system to be executed to handle the event. Events which will trigger an exception include:
Most but not all interrupts can be masked -- temporarily turned off -- either in the CPU or in the PIC/APIC.
Many debugging tools use a software interrupt for single-stepping through a program - for example, on a 6502, the instruction after the one to be executed by single-stepping is replaced with a BRK instruction (opcode 00), so that control will immediately return to the debugger after one instruction is executed. In other cases, the debugger regains control by scheduling a timer-based hardware non-maskable interrupt (NMI) to occur during the execution of the next instrution, using a peripheral timer chip.
== Multiple Cores ==
