For example, when evaluating a compound arithmetic function on a CPU that has two integer units capable of addition which take an average of 2 [[Clock|clock cycles]] to perform an operation, and a floating point multiplication unit which takes an average of 5 clock cycles to perform an operation, two multiplications in succession will cause a pipeline stall, because the second operation cannot be performed until the first multiplication has completed. With out-of-order execution, additional logic in the early portion of the pipeline could rearrange operations so that some integer add/subtract operations would be performed between the two multiplications, avoiding the stall (and therefore increasing performance).