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= Analyzing False Sharing and Ways to Eliminate False Sharing =
== Team Members ==
# [mailto:hnaidu@myseneca.ca?subject=DPS921 Harika Naidu]
# [mailto:msivanesan4@myseneca.ca?subject=DPS921 Mithilan Sivanesan]
# [mailto:hnaidu@myseneca.ca;msivanesan4@myseneca.ca?subject=DPS921 eMail All]
== Introduction ==
'''What is False Sharing (aka cache line ping-ponging)?''' <br>
False Sharing is one of the sharing pattern that affect performance when multiple threads share data. It arises when at least two threads modify or use data that happens to be close enough in memory that they end up in the same cache line. False sharing occurs when they constantly update their respective data in a way that the cache line migrates back and forth between two threads' caches.
In this article, we will look at some examples that demonstrate false sharing, tools to analyze false sharing, and the two coding techniques we can implement to eliminate false sharing.
=Cache Coherence=
In Symmetric Multiprocessor (SMP)systems , each processor has a local cache. The local cache is a smaller, faster memory which stores copies of data from frequently used main memory locations. Cache lines are closer to the CPU than the main memory and are intended to make memory access more efficient. In a shared memory multiprocessor system with a separate cache memory for each processor, it is possible to have many copies of shared data: one copy in the main memory and one in the local cache of each processor that requested it. When one of the copies of data is changed, the other copies must reflect that change. Cache coherence is the discipline which ensures that the changes in the values of shared operands(data) are propagated throughout the system in a timely fashion.
False sharing is a well-know performance issue on SMP systems, where each processor has a local cache. it occurs when treads on different processors modify varibles that reside on th the same cache line like so.
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[[FileMedia:CPUCacheline.png]]
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The frequent coordination required between processors when cache lines are marked ‘Invalid’ requires cache lines to be written to memory and subsequently loaded. False sharing increases this coordination and can significantly degrade application performance.