* w0 through w30 - for 32-bit-wide access (same registers - upper 32 bits are either cleared on loador sign-extended (set to the value of the most significant bit of the loaded value)).

Usage during [[Syscalls|syscall]]/function call:* '''r0-r7 are used for arguments and return values; additional arguments are on the stack'''

* '''The called routine is expected to save preserve r19-r28*** These registers are generally safe to use in your program.'''

These instructions are sufficient to complete the [[SPO600 Assembler Lab]]:; remember to replace the generic register names with ones that specify width (for example, replace "r0" with "x0" or "w0").

add r0,r1,r2 // load r0 with r1+r2 add r0,r1,99 // load r0 with r1+99 adr r0,''label'' // load r0 with the address ''label'' (this actually calculates an address from the [[Register#Program Counter|PC]] plus an offset) beq adrp r0,''label'' // load r0 with the 4K page containing ''label'' (this calculates an address from the [[Register#Program Counter|PC]] plus an offset, and is often followed by an ADD instruction so that the register points exactly to the ''label'') bl ''label'' // branch (with link) to label - this is a procedure / subroutine / function call br ''label'' // branch to label- this is a goto br ''register' ' // branch to the address in register b.eq ''label'' // branch to label if equal bne b.ne ''label'' // branch to label if not equal blt b.lt ''label'' // branch to label if less bgt b.gt ''label'' // branch to label if greater cmp r0,r1 // compare register r0 with register r1. The comparison sets flags in the processor status register which affect conditional branches. cmp r0,99 // compare the number 99 with register r0. The comparison sets flags in the processor status register which affect conditional branches. ldr r0,[r1,0] // load register r0 from the address pointed to by (r1 + (0 * ''size'')) where ''size'' is 8 bytes for 64-bit stores, 4 bytes for 32-bit stores ldr w0,[r1,0] // like ldr above but reads one byte 32 bits only - note the use of w0 instead of r0 for the source register name ldrb w0,[r1,0] // like above but reads 1 byte (8 bits) only - note the use of w0 for the source register name ldur r0,[r1,0] // load register r0 from the address pointed to by (r1 + 0) - the mnemonic means "load ''unscaled'' register" mov r0,r1 // move data from r1 to r0 mov r0,99 // load r0 with 99 (only certain immediate values are possible) ret // return from subroutine (counterpart to bl) str r0,[r1,0] // store register r0 to address pointed to by (r1 + (0 * ''size'')) where ''size'' is 8 bytes for 64-bit stores strb w0,[r1,0] // like str but writes one byte only - note the use of w0 instead of r0 for the source register name stur r0,[r1,0] // store register r0 to the address pointed to by (r1 + 0) - the mnemonic means "store ''unscaled'' register" svc 0 // perform a syscall msub r0,r1,r2,r3 // load r0 with r3-(r1*r2) (useful for calculating remainders) madd r0,r1,r2,r3 // load r0 with r3+(r1*r2) mul r0,r1,r2 // load r0 with r1*r2 (actually an alias - see ARM ARM) push r0 // push r0 onto the stack pop r0 // pop r0 off the stack udiv r0,r1,r2 // unsigned - divide r1 by r2, places quotient into r0 - remainder is not calculated (use msub)

* Destinations are given as the first argument (mov r0, r1 moves INTO r0 FROM r1; you can think of this as r0=r1).* For the LDR/STR instructions: you can append a character indicating the number of bits (lowest) to be loaded or stored:** Q = Quadword = 64 bits** D = Double word = 32 bits** W = Word = 16 bits** B = Byte = 8 bits

** Instruction Set and Software Developer Manual: [http://infocenterdeveloper.arm.com/helpARM Developer Information Centre]*** [https:/index.jsp?topic=/comdeveloper.arm.doccom/docs/den0024/latest ARM Cortex-A Series Programmer’s Guide for ARMv8-A]*** The ''short'' guide to the ARMv8 instruction set: [https://www.element14.genc010197acom/community/servlet/JiveServlet/previewBody/index41836-102-1-229511/ARM.htmlReference_Manual.pdf ARMv8 Instruction Set Overview] ("ARM ISA Overview")** Procedure call reference* The ''long'' guide to the ARMv8 instruction set: http[https://infocenterdeveloper.arm.com/helpdocs/topicddi0487/latest/com.arm.doc.ihi0055b/IHI0055B_aapcs64.pdfhttp-architecture-reference-manual-armv8-for-armv8-a-architecture-profile ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile] ("ARM ARM")** [https://wwwdeveloper.intelarm.com/contentdocs/wwwihi0055/uslatest/en/processors/architecturesprocedure-call-standard-for-the-arm-64-softwarebit-developerarchitecture Procedure Call Standard for the ARM 64-manuals.htmlbit Architecture (AArch64)]