* RandomMemory, including random-access memory (RAM), which consists of multiple [[Word|words]] of memory which are individually [[Address|addressable]] -- words can be individually written to or read from each address. Memory is used to store both instructions and data. Memory is generally [[Volatile|volatile]], but some non-volatile memory is usually provided for system startup. * Some memory may be is connected to two the CPU as well as one or more devices for "memory mapped" input/output -- the CPU as one device, and a peripheral such as a video system or disk controller as the second device.Most modern computers use a [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka11516.html Von Neuman] architecture, with one memory space for both instructions (software) and data. In some systems, devices may be accessed through a separate address range (designated for I/O ports), which acts like memory-mapped I/O but has a distinct addressing scheme. Devices can get the CPU's attention using an [[Computer_Architecture#Interrupts_and_Exceptions|Interrupt]] scheme. Devices include:** Storage, which is addressable in sectors or blocks, and is used for [[Volatile|non-volatile]], long-term storage of instructions and data.* I/O ports * Human interface devices (HID), such as keyboards, pointing devices (mice, touchscreens, trackpads, and so forth), and busesfingerprint readers. These are typically low-speed devices (e.g., people type at 6 characters per second or less).** Video, used which typically uses a region of memory as a framebuffer to connect store the image being displayed. The video system may also be able to peripheralsperform hardware-accelerated operations such as bit-blitting, fills, video overlays, and 3D operations.** Audio, which typically uses a region of memory as an audio sample buffer.** Connectivity, including network, serial, and radio (including WiFi and Cellular) connections.

* '''Register width''' - [[Register|Registers typically vary in ]] are generally fixed-width, with 8, 16, 32, and 64 bit widths common (though other values are sometimes seen). Some CPUs have multiple registers of different sizes, or can access smaller subsets of larger registers (e.g., accessing the first 8 bits of a 64-bit register when needed), or can access a register as two smaller registers or one larger register (e.g., the 16-bit accumulator register on the 6809E processor can also be accessed as two 8-bit registers). Processors with wider registers are generally considered more powerful, though this may actually be a drawback in some specific situations.* The '''number of registers''' varies from three or four to many dozen. Some processors are equipped with multiple sets of registers, and can rapidly switch between the register sets on demand (e.g., Intel "Hyperthreading" technology), which simplifies and speeds up process or thread switches. Since registers are often significantly faster than RAM, a larger register set is generally considered better, except that it will take longer to save a larger register set when switching processes. The full set of registers available on a CPU is known as the ''register file''.* The ''work'' of a CPU is performed by '''Execution Units''', which perform operations such as loading and storing data from/to memory (load/store unit), performing integer math (integer unit), executing [[Bitwise Operations|bitwise operations]], and performing floating-point math (floating-point unit, or FPU). The length of time taken to perform an operation varies according to the sophistication of the execution unit and the complexity of the operation. For example, a multiplication can be performed in many different ways, ranging from repeated addition (very slow, but requiring very little hardware logic) to table lookup (very fast, but requiring a lot of silicon), with most operations implementations falling somewhere in the middle. A multiplication will almost always take longer to perform than an addition, and may vary according to carry and overflow sub-operations required. The use of multiple units permits faster operations to be completed on some execution units while other (slower) operations are taking place on other execution units.* As instructions are performed, special results are recorded as '''[[Flags|flags]]''' within the CPU. For example, adding or multiplying two numbers will set a "Carry" flag when the result overflows the word width. Other flags may indicate zero or negative result values. These flags can then be used in later operations -- for example, a branch may be taken if the carry flag is set. The number of flags, their specific meanings, and the circumstances under which they are set (to binary "1") and cleared (to binary "0") vary from architecture to architecture.* '''Cache''' is high-speed memory placed between RAM and the CPU. This memory is faster than main RAM but much smaller; it improves performance by enabling the CPU to continue to write data quickly and continue without waiting for the data to be written out to main RAM. It also provides fast access to instructions or data that are accessed repeatedly, such as when a small loop is being executed. The performance difference between a loop that fits into cache and a loop that does not fit into cache can be substantial. Cache memory is arranged in "lines" which are typically a multiple of the word size; requesting a memory address that is not in cache results in a "cache miss" which causes a stall while the cache contents are retrieved from main memory. Cache design varies in many details, especially in write behaviour -- the cache can simply carry a write through to main memory (write-through), or it can hold the data in cache and write it back at a later time (write-back). There may be multiple levels of cache of varying sizes.* '''Pre-fetching''' is the process of retrieving instructions from memory before executing them. Done effectively, this avoids pipeline stalls due to cache misses.

* '''Pipelining''' is the sequential decoding and execution of an instruction. As each instruction is passed through the stages of a pipeline, other instructions can be processed by other stages. However, when a conditional branch appears, a decision must be made ''before the conditional branch can be evaluated'': should the pipeline be filled with the instructions that are on the code path associated with taking the branch, or with not taking the branch? In either case, if the wrong branch prediction is made, then the contents of the entire pipeline must be discarded. The pipeline can be stalled if an execution unit is not available when needed or if a memory read or write is stalled by cache. Execution based on branch prediction is called ''speculative execution''.

Effectively, memory is divided into "pages" of a set size (such as 4kb4KB, 1MB, or 4MB). These pages are ''mapped'' using a memory mapping table or address translation table, which renumbers the addresses of the locations within that page. Pages which do not appear in the memory map are not accessible to the CPU. It is also possible to mark specific attributes for each page in the mapping table, such as "do not execute" and "read only".

For example, a computer may have three processes, "A", "B", an and "C". Only one process is active at a time (assuming a single-core model), and the operating system switches between the processes frequently whenever they are eligible to run to create the illusion appearance of multi-taskingconcurrent execution. (A program is not eligible to run if it is blocked by something -- for example, when it is waiting for data from the disk, network, or keyboard, and that data hasn't arrived yet).

Process B and C may be executing the same program. In this casescase, the memory map active while each process is running contains the same program, but different data pages. The program is only loaded into memory once, reducing memory requirements.

Hardware interrupt requests (IRQs) are external electrical signals which cause the CPU to stop executing the current program (generally between instructions) and jump to a pre-defined block of code. This These signals were originally dedicated electrical signals but in newer systems may take the form of serially-signalled data (for example, on a PCIe bus). An interrupt is typically used to make the operating system service I/O requests as soon as when they occur. For example, when a sector of data is available from a disk drive, the disk controller will trigger an interrupt on the CPU, which will cause the operating system to load the received data. This may then cause the operating system to change the status of a processed process from blocked (waiting for data) to eligible for execution, so that it will be considered along with all other eligible processes when the next process switch is performed.

Most architectures support multiple levels of interrupts, usually numbered (e.g., "IRQ0", "IRQ8", and so forth). These may be handled by the CPU itself, or a (programmable) interrupt controller (''PIC'' , ''APIC'', or ''APICGIC'') may latch the IRQ event and signal the processor, which then queries the interrupt controller to determine which interrupt occurred. Some architectures support multiple types of levels or priorities of interrupts -- for example, the 6502 supports regular (IRQ) and higher-priority non-maskable interrupts (NMI), while ARM processors offer both regular (IRQ) and "fast" interrupts (FIQ).

* Accessing a memory location which is not mapped. This will cause the operating system to swap-in a virtual memory page, load a binary page on-demand, or signal a segmentation fault (segfault)/general protection fault (gpf) depending on the circumstances.

* Attempted execution of an undefined or invalid instruction.

When any type of interrupt is received, the [[Register#Program Counter|program counter ]] is saved (typically pushed by pushing it on the [[Stack|stack]] or storing it in a dedicated register), and then a new value for the program counter is loaded from an ''interrupt vector'' stored in a register or a pre-defined memory location, usually at the top of or bottom of physical [[Address|address space]]. Effectively, this means that a subroutine jump is performed to the interrupt-handling routine. In systems where multiple devices are connected to one hardware interrupt line, it is necessary to poll the PIC/APIC or the attached devices to determine which one(s) triggered the interrupt before servicing the request(s). When the interrupt routine exits, the original program counter location is restored, and execution of the interrupted program continues.

Most but not all interrupts can be masked -- temporarily turned off -- either in the CPU or in the PIC/APIC/GIC.

Many debugging tools use a software interrupt for single-stepping through a program - for example, on a 6502, the instruction after the one to be executed by single-stepping is replaced with a BRK instruction (opcode 00), so that control will immediately return to the debugger after one instruction is executed. In other cases, the debugger regains control by scheduling a timer-based hardware non-maskable interrupt (NMI) to occur during the execution of the next instrutioninstruction, using a peripheral timer chip.

There are alternate approaches alternatives to SMP, including non-uniform memory access (NUMA).

For example, when evaluating a compound arithmetic function on a CPU that has two integer units capable of addition which take an average of 2 [[Clock|clock cycles ]] to perform an operation, and a floating point multiplication unit which takes an average of 5 clock cycles to perform an operation, two multiplications in succession will cause a pipeline stall, because the second operation cannot be performed until the first multiplication has completed. With out-of-order execution, additional logic in the early portion of the pipeline could rearrange operations so that some integer add/subtract operations would be performed between the two multiplications, avoiding the stall (and therefore increasing performance).

Out-of-order execution required requires significant additional hardware logic (chip space) and energy.

RISC stands for ''Reduced Instruction Set Computer'' and is a design philosophy favouring a CPU design which executes a small number of simple instructions very quickly. This approach emphasizes the importance of the relies on a good compiler to sequence instructions optimally. Since each instruction is simpler, less silicon is required for instruction decoding and execution, and therefore more silicon is devoted to execution units, cache, and registers to improve performance.

CISC stands for ''Complex Instruction Set Computer'' and is an alternate design philosophy which favours a CPU design where each instruction can perform a lot of work. This approach emphasizes chip logic to optimize performance. Additional sillicon silicon is needed for features such as instruction resequencing, deep pipelines, and more complex execution units.

The RISC vs. CISC debate was at its peak in the 1980s and early 1990s. Most modern CPU designs combine elements of both philosophies. For example, ARM processors, which have historically been considered RISC designs, now include out-of-order execution (a CISC feature); x86 processors (, traditionally regarded as a CISC design) , now feature larger register sets that were originally considered a RISC feature.

The [[Instruction Set Architecture]] specifies the encoding of instructions. This is specific to a particular architecture family and therefore dependent on certain architectural features, such as the register set, but independent of other features, such as the cache type -- because the cache type affects performance but not the instructions which can be executed by the CPU.

Most processors use a [[Word|word]] size that is multiple of width of some common data types . However, it is often necessary to access data which is a fraction of this size -- for example, a system with a 32-bit [[Word#Hardware Word|hardware word size]] that is running applications which use UTF-8 character encoding may often need to read or write single [[Word#Byte|bytes]] of data. A byte-sized read will cause the CPU to perform a 32-bit read, followed by [[Bitwise Operations|masking and shifting operations]] to extract the desired byte from the 32-bit word. A single-byte write operation will cause the CPU to read the existing word, extract the unaffected bits within that word, (similar to an [[Bitwise Operations#ORAND|AND]] operation), merg in the new value(similar to an [[Bitwise Operations#OR|OR]] operation), and then write the word back to memory.

Unaligned memory access causes similar issues. For example, to read a 32-bit value from the byte address 0x2, most 32-bit CPUs will read a 32-bit value starting at byte address 0x0 and perform an [[Bitwise Operations|AND]] to extract highest 16 bits, then a shift to move those bits to the lowest 16 bit positions. The CPU will then read a 32-bit value starting at byte address 0x4, perform the equivalent of an AND to extract the lowest 16 bits, shift those bits to the highest 16 bit positions, and then OR the high 16 bits and the low 16 bits together into a single 32 bit value. These operations are usually hardware-optimized to occur much faster than the equivalent software operations. (Writing an unaligned 32-bit value is even worsethan reading it!)

Some processors , such as ARMv5 processors, do not have alignment-fixup hardware, and an unaligned access causes a processor exception. The operating system may ignore the unaligned access (usually leading to incorrect results), stop the program performing the unaligned access, or fix up the access in software and then resume execution of the process which caused the exception.

On a Linux system, the control file <code>/proc/cpu/alignment </code> controls how the operating system will handle alignment exceptions (on machines which lack alignment-fixup hardware). The possible values are:

Most modern compilers, such as gccGCC, enable you to set the overall target architecture, but also permit you to optimize performance for a specific CPU model within that target architecture. For example, with GCC, the <code>-march</code> argument selects the target architecture for the output code and the specific features that may be accessed by that code, while <code>-mtune</code> is used to optimize the performance for a particular CPU variant.