* '''Status registers''' (or Flag registers, or Condition code registers) contain flag bits, which are set/cleared/tested either explicitly (by instructions) or implicitly (as the result of other operations). For example, the ARM aarch32 "Z" flag is set ("1") if an operation has a non-zero result, and cleared ("0") if an operation has a non-zero result. This flag is one bit within the Application Processor Status Register (APSR).

* '''Control registers''' alter the operation of the processor, such as by enabling binary coded decimal (BCD) math or toggling [[Endian|little-endian/big-endian]] mode.