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→Interrupts and Exceptions
Hardware interrupt requests (IRQs) are external electrical signals which cause the CPU to stop executing the current program (generally between instructions) and jump to a pre-defined block of code. This is typically used to make the operating system service I/O requests as soon as they occur. For example, when a sector of data is available from a disk drive, the disk controller will trigger an interrupt on the CPU, which will cause the operating system to load the received data. This may change the status of a processed from blocked (waiting for data) to eligible for execution, so that it will be considered along with all other eligible processes when the next process switch is performed.
Most architectures support multiple levels of interrupts, usually numbered (e.g., "IRQ0", "IRQ8", and so forth). These may be handled by the CPU itself, or a (programmable) interrupt controller (''PIC'' or ''APIC'') may latch the IRQ event and signal the processor, which then queries the interrupt controller to determine which interrupt occurred. Some architectures support multiple types of levels of interrupts -- the 6502 supports regular (IRQ) and higher-priority non-maskable (NMI) interrupts, while ARM processors offer both regular (IRQ) and "fast" interrupts (FIQ).
Software interrupts are similar to hardware interrupts, but are triggered by a specific instruction on certain architectures. x86 processors use software interrupts to invoke system calls.
Exceptions (or ''traps'') are similar to interrupts, but are triggered by event occurrences within the processor. These exceptions cause code within the operating system to be executed to handle the event. Events which will trigger an exception include:
* Accessing a memory location which is not mapped. This will cause the operating system to swap-in a virtual memory page, load a binary page on-demand, or segmentation fault (segfault)/general protection fault (gpf) depending on the circumstances.
* Writing to a read-only page, which will cause a copy-on-write or segfault/gpf depending on circumstances.
* Attempted execution of a protected instruction. Some operations can only be used when the CPU is in a particular mode -- for example, MMU address translation tables can only be altered by the operating system kernel, not by a regular process.
* Attempted execution of an undefined instruction.
When any type of interrupt is received, the program counter is typically pushed on the stack, and then the program counter is loaded from an ''interrupt vector'' stored in a register or a pre-defined memory location, usually at the top of bottom of physical address space. Effectively, this means that a subroutine jump is performed to the interrupt-handling routine. In systems where multiple devices are connected to one hardware interrupt line, it is necessary to poll the PIC/APIC or the attached devices to determine which one(s) triggered the interrupt before servicing the request(s).
Most but not all interrupts can be masked -- temporarily turned off -- either in the CPU or in the PIC/APIC.
== Multiple Cores ==