6502 Instructions - Introduction
It is still under construction and content may change. Do not rely on this information.
The 6502 processor has a compact instruction set, consisting of just 56 instructions:
ADC AND ASL BCC BCS BEQ BIT BMI BNE BPL BRK BVC BVS CLC
CLD CLI CLV CMP CPX CPY DEC DEX DEY EOR INC INX INY JMP
JSR LDA LDX LDY LSR NOP ORA PHA PHP PLA PLP ROL ROR RTI
RTS SBC SEC SED SEI STA STX STY TAX TAY TSX TXA TXS TYA
This page groups these instructions and explains their basic function.
Addressing Modes
There are 13 6502 Addressing Modes. All of these instructions work with at least one addressing mode, and many work with several addressing modes. See the Resources section for Opcode tables that define which instructions work with which addressing modes.
Performance
Each 6502 instruction takes a defined number of machine cycles to execute. In some cases,the number of cycles will vary depending on the circumstances of the instruction's execution - for example, the conditional branch instruction BRE (Branch if EQual) takes:
- 2 cycles if the branch is not taken
- 3 cycles if a branch is taken to an address in the same page
- 4 cycles if a branch is taken to an address in another page
Remember that the Program Counter (PC register) contains a pointer to the next instruction to be executed. When the BEQ instruction has been loaded into the CPU, the PC points to the instruction following the BEQ. The branch works by adding a signed integer value (in the range of -128 to +127) to the Program Counter; the extra cycle required when the branch is taken is used to process the addition. If the high byte of the Program Counter changes (because the branch crosses in to another page), one additional cycle is required to adjust the high byte.
You can find the execution time in the instruction charts found in the Resources section below.
To convert the number of cycles to time, multiply the cycles by the time between system clock pulses. Many 6502 systems operated at 1 MHz (1 million operations per second), and therefore 1 cycle corresponded to 1 millionth of a second, or 1 microsecond (uS). Therefore, an instruction that took 4 clock cycles would take 4 uS to execute.
Loading and Storing Data (to/from Memory)
Register-Memory Loads and Stores
There are three instructions to load data from memory to a register:
LDA ; load the accumulator LDX ; load the X register LDY ; load the Y register
And there are three matching instructions to store data from a register to a memory location:
STA ; store the accumulator STX ; store the X register STY ; store the Y register
Push/Pull on the Stack
When a value is pushed to the stack, the stack pointer register (SP) is decremented and the selected register is written to memory location $0100+SP.
When a value is pulled from the stack, the stack pointer register (SP) is incremented and the selected register is loaded from memory location $0100+SP.
There are two instructions to push data onto the stack:
PHA ; push the accumulator PHP ; push the processor status register
And two matching instructions to pull data from the stack:
PLA ; pull the accumulator PLP ; pull the processor status register
Note that some other operations, such as JSR, interrupts, RTI, and RTS, cause data to be pushed to or pulled from the stack.
Bitwise Operations
Arithmetic
ADC ; add with carry
The accumulator + memory location + carry flag is stored to the accumulator (A = A + M + C).
The carry flag can be used to carry overflow information from the lowest byte to the highest byte of a multi-byte addition. Clear the carry flag and then add the lowest bytes, then leave the carry flag untouched and add the second-lowest bytes. Continue to the highest byte in the multi-byte sequence.