Winter 2018 SPO600 Weekly Schedule
This is the schedule and main index page for the SPO600 Software Portability and Optimization course for Winter 2018.
This SPO600 weekly schedule will be updated as the course proceeds - dates and content are subject to change. The cells in the summary table will be linked to relevant resources and labs as the course progresses.
Schedule Summary Table
This is a summary/index table. Please follow the links in each cell for additional detail which will be added below as the course proceeds -- especially for the Deliverables column.
Evaluation
| Category | Percentage | Evaluation Dates |
|---|---|---|
| Communication | 20% | January (up Feb 4, 5%), End of February (5%), End of March (5%), end of course (April 21 - 5%). |
| Quizzes | 10% | May be held during any class, usually at the start of class. A minimum of 5 one-page quizzes will be given. No make-up/retake option is offered if you miss a quiz. Lowest 3 scores will not be counted. |
| Labs | 10% | See deliverables column above. All labs must be submitted by April 21, but it is best if you stay on top of the labs and submit according to the table above. |
| Project work | 60% | 3 stages: 15% (date TBA), 20% (date TBA), 25% (April 21). |
Week 1
Week 1 - Class I
Introduction to the Problems
Porting and Portability
- Most software is written in a high-level language which can be compiled into machine code for a specific computer architecture. In many cases, this code can be compiled for multiple architectures. However, there is a lot of existing code that contains some architecture-specific code fragments written in Assembly Language (or, in some cases, machine-specific high-level code).
- Reasons for writing code in Assembly Langauge include:
- Performance
- Atomic Operations
- Direct access to hardware features, e.g., CPUID registers
- Most of the historical reasons for including assembler are no longer valid. Modern compilers can out-perform most hand-optimized assembly code, atomic operations can be handled by libraries or compiler intrinsics, and most hardware access should be performed through the operating system or appropriate libraries.
- A new architecture has appeared: AArch64, which is part of ARMv8. This is the first new computer architecture to appear in several years (at least, the first mainstream computer architecture).
- At this point, most key open source software (the software typically present in a Linux distribution such as Ubuntu or Fedora, for example) now runs on AArch64. However, it may not run as well as on older architectures (such as x86_64).
Benchmarking and Profiling
Benchmarking involves testing software performance under controlled conditions so that the performance can be compared to other software, the same software operating on other types of computers, or so that the impact of a change to the software can be gauged.
Profiling is the process of analyzing software performance on finer scale, determining resource usage per program part (typically per function/method). This can identify software bottlenecks and potential targets for optimization.
Optimization
Optimization is the process of evaluating different ways that software can be written or built and selecting the option that has the best performance tradeoffs.
Optimization may involve substituting software algorithms, altering the sequence of operations, using architecture-specific code, or altering the build process. It is important to ensure that the optimized software produces correct results and does not cause an unacceptable performance regression for other use-cases, system configurations, operating systems, or architectures.
The definition of "performance" varies according to the target system and the operating goals. For example, in some contexts, low memory or storage usage is important; in other cases, fast operation; and in other cases, low CPU utilization or long battery life may be the most important factor. It is often possible to trade off performance in one area for another; using a lookup table, for example, can reduce CPU utilization and improve battery life in some algorithms, in return for increased memory consumption.
Most advanced compilers perform some level of optimization, and the options selected for compilation can have a significant effect on the trade-offs made by the compiler, affecting memory usage, execution speed, executable size, power consumption, and debuggability.
Build Process
Building software is a complex task that many developers gloss over. The simple act of compiling a program invokes a process with five or more stages, including pre-proccessing, compiling, optimizing, assembling, and linking. However, a complex software system will have hundreds or even thousands of source files, as well as dozens or hundreds of build configuration options, auto configuration scripts (cmake, autotools), build scripts (such as Makefiles) to coordinate the process, test suites, and more.
The build process varies significantly between software packages. Most software distribution projects (including Linux distributions such as Ubuntu and Fedora) use a packaging system that further wraps the build process in a standardized script format, so that different software packages can be built using a consistent process.
In order to get consistent and comparable benchmark results, you need to ensure that the software is being built in a consistent way. Altering the build process is one way of optimizing software.
Note that the build time for a complex package can range up to hours or even days!
General Course Information
- Course resources are linked from the CDOT wiki, starting at http://wiki.cdot.senecacollege.ca/wiki/index.php/SPO600 (Quick find: This page will usually be Google's top result for a search on "SPO600").
- Coursework is submitted by blogging.
- Quizzes will be short (1 page) and will be held without announcement at any time, generally at the start of class. Your lowest three quiz scores will not be counted, so do not worry if you miss one or two.
- Course marks (see Weekly Schedule for dates):
- 60% - Project Deliverables
- 20% - Communication (Blog and Wiki writing)
- 20% - Labs and Quizzes (10% labs - completed/not completed; 10% for quizzes - lowest 3 scores not counted)
- All classes will be held in an Active Learning Classroom -- you are encouraged to bring your own laptop to class. If you do not have a laptop, consider signing one out of the Learning Commons for class, or using a smartphone with an HDMI adapter.
- For more course information, refer to the SPO600 Weekly Schedule (this page), the Course Outline, and SPO600 Course Policies.
Week 1 - Class II
Course and Setup: Accounts, agreements, servers, and more
- SPO600 Communication Tools
- Winter 2018 SPO600 Participants page
- Key generation for SSH to the SPO600 Servers.
- Student Agreement
Discussion of how open source communities work
- Background for the Code Review Lab (Lab 1).
Week 1 Deliverables
- Course setup:
- Set up your SPO600 Communication Tools - in particular, set up a blog and add it to Planet CDOT (via the Planet CDOT Feed List).
- Add yourself to the Winter 2018 SPO600 Participants page (leave the projects columns blank).
- Generate a pair of keys for SSH and email the public key to your professor, so that he can set up your access to the class servers.
- Sign and return the Open Source Professional Option Student Agreement (this will be done on paper in class).
- Optional (recommended): Set up a personal Fedora system.
- Optional: Purchase an AArch64 development board (such as a 96Boards HiKey or Raspberry Pi 3. If you use a Pi, install a 64-bit Linux operating system on it, not a 32-bit version).
Week 2
Week 2 - Class I
- Binary Representation of Data
- Numbers
- Integers
- Fixed-point numbers
- Floating-point numbers
- Characters
- ASCII
- ISO8859-1
- Unicode
- Encoding schemes
- EBCDIC
- Images
- Sound
- Numbers
- Computer Architecture overview (see also the Computer Architecture Category)
- A first look at the x86_64 and AArch64 Architectures and ISA
- Register file comparison
- Instruction encoding
- ELF
- Procedure calling conventions
Reference
- Computer Architecture and Computer Architecture Category
- Aarch64 Register and Instruction Quick Start
- x86_64 Register and Instruction Quick Start
Week 2 - Class II
- Compiler Operation
- Stages of Compilation
- Preprocessing
- Compiling
- Assembling
- Linking
- Stages of Compilation
- Analyzing compiler output
- Disassembly
- Compiled C Lab (Lab 2)
Week 2 Deliverables
- Blog your conclusion to the Code Review Lab (Lab 1)
- Blog the results and conclusion from the Compiled C Lab (Lab 2)
Week 3
Week 3 - Class I
Week 3 - Class II
-
Complete Lab 3Class cancelled
Week 3 Deliverables
- Blog your initial experience on the Assembler Lab (Lab 3).
Week 4
Week 4 - Class I
- Continue work in class on the Assembler Lab (Lab 3).
Week 4 - Class II
- Continue work in class on the Assembler Lab (Lab 3).
Week 4 Deliverables
- Blog your Lab 3 results.
Week 5
Week 5 - Class I
Week 5 - Class II
- Advanced Compiler Optimizations
- Introduction to Vector Processing/SIMD
- Vectorization Lab (Lab 4) as homework
- Algorithm Selection Lab (Lab 5) in work groups
Week 5 Deliverables
- Blog your results for Lab 4 and Lab 5 -- be sure to include links to your code, detailed results, and your reflection on the lab.
Week 6
Week 6 - Class I
- Inline Assembly Language -- often used for:
- Implementing a memory barrier
- Performing an Atomic Operation
- Atomics are operations which must be completed in a single step (or appear to be completed in a single step) without potential interruption.
- Wikipedia has a good basic overview of the need for atomicity in the article on Linearizability
- Gaining performance (by accessing processor features not exposed by the high-level language being used (C, C++, ...))
- Inline Assembler Lab (Lab 6)
Week 6 - Class II
- Processor Addressing Modes
- Navigating CPU technical documentation
- A (very) quick intro to GDB
- Project: Selecting, Building, Benchmarking, and Profiling
Week 6 Deliverables
- Blog your Lab 5 and 6 results.
- Start blogging about your project.
- Reminder: Blogs will be marked as they stand at 11:59 on March 4, the Sunday at the end of Reading Week.
Week 7
Week 7 - Class I
- Project Discussion
Week 7 - Class II
Week 7 Deliverables
- Complete your Stage I project posts on your blog.
Week 8
Week 8 - Class I
- Sysadmin for Developers
- Project Discussion
Week 8 - Class II
Overview/Review of Processor Operation
- Fetch-decode-dispatch-execute cycle
- Pipelining
- Branch Prediction
- In-order vs. Out-of-order execution
- Micro-ops
Memory Basics
- Organization of Memory
- System organization
- Process organization
- Text, data
- Stack
- Heap
- Memory Speeds
- Cache
- Cache lookup
- Cache synchronization and invalidation
- Cache line size
- Prefetch
- Prefetch hinting
Memory Architecture
- Virtual Memory and Memory Management Units (MMUs)
- General principles of VM and operation of MMUs
- Memory protection
- Unmapped Regions
- Write Protection
- Execute Protection
- Privilege Levels
- Swapping
- Text sharing
- Data sharing
- Shared memory for Inter-Process Communication
- Copy-on-Write (CoW)
- Demand Loading
- Memory mapped files
Memory Barriers
Memory Barriers ensure that memory accesses are sequenced so that multiple threads, processes, cores, or IO devices see a predictable view of memory.
- Leif Lindholm provides an excellent explanation of memory barriers.
- Blog series - I recommend this series, especially the introduction, as a very clear explanation of memory barrier issues.
- Presentation at Embedded Linux Conference 2010 (Note: Acquire/Release in C++11 and ARMv8 aarch64 appeared after this presentation):
- Memory Barriers - A Hardware View for Software Hackers - This is a highly-rated paper that explains memory barrier issues - as the title suggests, it is designed to describe the hardware origin of the problem to software developers. Despite the fact that it is an introduction to the topic, it is still very technical.
- ARM Technical Support Knowlege Article - In what situations might I need to insert memory barrier instructions? - Note that there are some additional mechanisms present in ARMv8 aarch64, including Acquire/Release.
- Kernel Documentation on Memory Barriers - discusses the memory barrier issue generally, and the solutions used within the Linux kernel. This is part of the kernel documentation.
- Acquire-Release mechanisms
- MSDN Blog Post with a very clear explanation of Acquire-Release.
- Preshing on Programming post with a good explanation.
- ARMv8 Instruction Set Architecture Manual (ARM InfoCentre registration required) - See the section on Acquire/Release and Load/Store, especially Load/Store Exclusive (e.g., LDREX)
The Future of Memory
- NUMA (on steroids!)
- Non-volatile, byte-addressed main memory
- Non-local memory / Memory-area networks
- Memory encryption
Software Impact
- Alignment checks
- Page boundary crossing
Week 8 Delivarables
- Blog about your project