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GPU621/DPS921 G P Index 20177

Revision as of 17:54, 14 December 2017 by Msivanesan4 (talk | contribs) (→‎Team False Sharing)


GPU621/DPS921 | Participants | Groups and Projects | Resources | Glossary

Please add an overview of your group here and create a separate project page for your group!

Project Rules

  1. Use the Group page for a Journal of your activities throughout the course of the project
  2. Project should cover material that differ from the material on the course web site
  3. Presentation can be in powerpoint or walkthru the group project page
  4. Link to the project page should be on the Participants table
  5. Presentation slots are first come first served
  6. Attendance at all presentations is mandatory - marks will be deducted for absenteeism
  7. Marks will be awarded for both Group Wiki page and for the Presentation

Sample Projects (Former Students)

  1. Winter 2016 semester
  2. Fall 2016 semester

Suggested Projects (each * denotes one group that has claimed this topic)

  1. Intel Parallel Studio Advisor - [Intel Site]
  2. Intel Parallel Studio Inspector - [Intel Site]
  3. Intel Parallel Studio vTune Amplifier - [Intel Site] *
  4. Intel Math Kernel Library* - [Intel Site]
  5. Intel Data Analytics Acceleration Library - [Intel Site] *
  6. Totalview Debugger - [Get Student License]
  7. OpenMP Debugging in Visual Studio - [MSDN Notes] *
  8. Debugging Threads in Intel Parallel Studio - [Dr Dobbs Article]
  9. Analyzing False Sharing - [Herb Sutter's Article]
  10. The Chapel Programming Language - [Chapel Site]
  11. Apache's Spark - [Spark Site]
  12. OpenMP Profiler - [ompP]
  13. C++11 Threads Library Comparison to OpenMP - Case Studies*
  14. C++11 STL Comparison to TBB - Case Studies*

Group and Project Index

You can find a sample project page template here

Sample Project

Project Title here

  1. Chris Szalwinski
  2. Fardad Soleimanloo
  3. eMail All


Team Hortons

Multithreading with Rust

  1. Henrique Salvadori Coelho
  2. Olga Belavina


Alpha Centauri

Intel® Data Analytics Acceleration Library

Group Members

  1. Joseph Pildush
  2. Rosario Cali
  3. eMail All

Progress

0%


Game of Threads

C++11 Threads Library Comparison to OpenMP - Case Studies

  1. Martin Ristov
  2. Van Chau Bui
  3. Joshua Longhi

Team MMD

Intel Math Kernel Library

Group Members

  1. Daniel Chang
  2. Mattew Nguyen
  3. Marko Radmanovic
  4. eMail All


Team Debug

OpenMP Debugging in Visual Studio

  1. Sofia Ngo-Trong
  2. Azusa Shimazaki
  3. Orlandson Asturiano
  4. eMail All

Team Go

Go Programming Language

  1. Suhaib Saqib
  2. Roana Almira
  3. Liam Newell
  4. eMail All

Team NP Complete

Quantum Tunneling Simulation

  1. Cassandra Laffan
  2. Jinnah Ali-Clarke
  3. eMail All


Team False Sharing

In symmetric multiprocessor systems (SMP), each processor has a local cahce. The memory system must guarantee cache coherence. False sharing occurs when threads on different processors modify variables that reside on the same cache line. This invalidates the cache line and forces an update, which hurts performance.

False sharing is a well-know performance issue on SMP systems, where each processor has a local cache. it occurs when treads on different processors modify varibles that reside on th the same cache line like so.

In Figure, threads 0 and 1 require variables that are adjacent in memory and reside on the same cache line. The cache line is loaded into the caches of CPU 0 and CPU 1. Even though the threads modify different variables, the cahche line is invalidatedm forcing a memory update to maintain cache coherency.

To ensure data consistency across multiple caches, multiprocessor-capable Intel® processors follow the MESI (Modified/Exclusive/Shared/Invalid) protocol. On first load of a cache line, the processor will mark the cache line as ‘Exclusive’ access. As long as the cache line is marked exclusive, subsequent loads are free to use the existing data in cache. If the processor sees the same cache line loaded by another processor on the bus, it marks the cache line with ‘Shared’ access. If the processor stores a cache line marked as ‘S’, the cache line is marked as ‘Modified’ and all other processors are sent an ‘Invalid’ cache line message. If the processor sees the same cache line which is now marked ‘M’ being accessed by another processor, the processor stores the cache line back to memory and marks its cache line as ‘Shared’. The other processor that is accessing the same cache line incurs a cache miss.

The frequent coordination required between processors when cache lines are marked ‘Invalid’ requires cache lines to be written to memory and subsequently loaded. False sharing increases this coordination and can significantly degrade application performance.

Analyzing False Sharing

  1. Harika Naidu
  2. Mithilan Sivanesan
  3. eMail All

Team Darth Vector

C++11 STL Comparison to TBB - Case Studies

  1. Alistair Godwin
  2. Leonel Jara
  3. Giorgi Osadze

Team Lion

Intel Parallel Studio vTune Amplifier

  1. Jagmeet Bhamber
  2. Shivam Gupta
  3. Yong Kuk Kim

Presentation Schedule

Team Name Date and Time
Team Hortons December 15 11:40
Game of Threads December 15 12:00
Team MMD December 15 12:20
December 15 12:40
December 15 13:00
Team Go December 18 13:30
December 18 13:50
Alpha Centauri December 18 14:10
Darth Vector December 18 14:30
Team False Sharing December 18 14:50
Team Debug December 22 11:40
Team Lion December 22 12:00
Team NP Complete December 22 12:20


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