Fedora ARM Secondary Architecture/SheevaPlug
Revision as of 15:13, 16 April 2010 by Apvlahopoulos (talk | contribs)
SheevaPlug Specifications
Sheeva CPU Core
1.2 GHz operation
L1 Cache: 16K Instruction + 16K Data
L2 Cache: 256KB
Memory
DDR2 400MHz, 16-bit bus
512MB DDR2: 1Gb x8, 4 devices
Power efficient Samsung devices
NAND FLASH Controller, 8-bit bus
512MB NAND FLASH: 4Gb x8, direct boot
128-bit eFuse Memory
Power Power input: 100-240VAC/50-60Hz 19W DC Consumption: 5V/3.0A High efficiency POL DC-DC converters
'Development Interface' System Development Board JTAG and Console Interface via USB SDIO expansion JTAG OpenOCD support via USB
'High speed I/O & Peripherals '
GE, USB 2.0 Host RTC w/ Battery UL/CE/FCC certified
Accessing SheevaPlug from a Windows box
Connecting to the Sheevaplug Using Windows
