Instruction Set Architecture

From CDOT Wiki
Revision as of 11:40, 26 September 2019 by Chris Tyler (talk | contribs)
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to: navigation, search

The Instruction Set Architecture of a processor is the set of instructions which that processor can execute, the addressing modes available, and the encoding of those instructions as machine code.

Retrieved from "https://wiki.cdot.senecapolytechnic.ca/w/index.php?title=Instruction_Set_Architecture&oldid=140880"