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[[Category:SBR600]][[Category:DPI908]][[Category:SPO600]]
''make'' is a specialized scripting language used to build software. Unlike most scripting languages, commands are not executed in linear (start-to-finish) sequence; instead, command sequences are defined in terms of what input they accept and what output they produce, and ''make'' automatically sequences the commands to produce the required output.
Running the <code>make</code> command by itself will execute the makefile script named <code>Makefile</code> or <code>makefile</code> in the current directory.
== Targets and Dependencies ==
Picture a very simple build, where the file <code>test.c</code> is compiled by ''gcc'' into the executable binary named <code>test</code>.
test.c -> compiled by the command 'gcctestgcc test.c -o test' -> test
The binary executable product file, <code>test</code>, is considered the ''target'' -- the object to be built. The file <code>test.c</code> is a dependency - a file that is required in order to produce the target. ''gcc'' is the command that builds the target from the dependency.
This is because the timestamp on the target (<code>test</code>) is later than the timestamp on the dependency (<code>test.c</code>). If the dependency has been changed since the target was built, though, then ''make'' will rebuild the target.
=== Complex Dependencies ===
A more complicated build will involve a number of targets and dependencies. C programs, for example, can be compiled into intermediate files, called object files (.o extension), which can then be combined to produce executables.
There are several things worth noting about this ''Makefile'':
# Variables are used for the name of the compiler and the compiler flags. This makes it very easy to change these values -- to use the ''gcc'' compiler, for example, the CC variable could simply be changed to ''gcc''. If variables were not used, you would have to change every line that invoked the compiler.
# ''all'' is a dummy target. Since it appears as the first target in the file, it is executed firstby default if no target is specified as an argument to the <code>make</code> command. It depends on the ''half'' and ''double'' files, which will be built in order to satisfy the dependency. However, the ''all'' target does not specify any commands, and the file <code>all</code> will never be built.
When ''make'' is executed the first time, five compilations are performed:
make: Nothing to be done for 'all'.
If the file <code>half.c</code> was edited or the datestamp last-modified timestamp (mtime) was updated, running ''make'' would execute two compilations:
$ touch half.c
On a large programming project, a binary may be comprised of hundreds or even thousands of source files, and compiling all of those files may take hours. If a software developer edits just one file, it's a waste of time to rebuild everything, so ''make'' can save a lot of time -- especially when the software is rebuilt many thousand times.
=== Fake Targets ===
It is not uncommon to include "fake" targets in a Makefile -- targets which never get built, but which perform a useful operation. For example, a target of "all" never produces an actual file named "all". Typical fake targets include:
* all: build all binaries
* docs: builts all documentation (e.g., generates PDFs, HTML, manpages, etc)
* install: install all files, building binaries, documentation, etc if required
* clean: erases all built intermediate and binary files
* dist-clean (or distclean): erases all files not included in the original distribution of the source
* check (or test): tests the software
The make command will exit as soon as any command pipeline fails, so fake targets which may non-fatally fail are usually forced to return a success code; for example, to delete files which may or may not exist as part of a "clean" target, code such as this may be used:
rm *.o || true
== Examples ==
* [http://matrix.senecacollege.ca/~chris.tyler/osd600/makefile-examples.tgz A tarball of simple Makefile examples]
